参数资料
型号: MT48H8M16LFB4-75:K TR
厂商: Micron Technology Inc
文件页数: 34/63页
文件大小: 0K
描述: IC SDRAM 128MBIT 133MHZ 54VFBGA
标准包装: 1
格式 - 存储器: RAM
存储器类型: 移动 SDRAM
存储容量: 128M(8Mx16)
速度: 133MHz
接口: 并联
电源电压: 1.7 V ~ 1.95 V
工作温度: 0°C ~ 70°C
封装/外壳: 54-VFBGA
供应商设备封装: 54-VFBGA(8x8)
包装: 标准包装
其它名称: 557-1531-6
128Mb: x16 Mobile SDRAM
Truth Tables
Table 7:
Truth Table 3 – Current State Bank n , Command to Bank n
Notes: 1–6; notes appear below table
Current State
Any
Idle
Row active
Read (auto
precharge
disabled)
Write (auto
precharge
disabled)
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS#
X
H
L
L
L
L
H
H
L
H
H
L
H
H
H
L
H
CAS#
X
H
H
L
L
H
L
L
H
L
L
H
H
L
L
H
H
WE#
X
H
H
H
L
L
H
L
L
H
L
L
L
H
L
L
L
Command (Action)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
Notes
7
7
8
9
9
10
9
9
10
11
9
9
10
11
Notes:
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2) and after
t XSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank
and the commands shown are those allowed to be issued to that bank when in that state.
Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
Row active:
The bank has been precharged, and t RP has been met.
A row in the bank has been activated, and t RCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COM-
MAND INHIBIT or NOP commands, or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Truth Table 3, and according to Truth Table 4.
Precharging:
Starts with registration of a PRECHARGE command and ends when
t RP
is met. Once t RP is met, the bank will be in the idle state.
Row activating:
Read w/auto
precharge enabled:
Write w/auto
precharge enabled:
Starts with registration of an ACTIVE command and ends when t RCD
is met. Once t RCD is met, the bank will be in the row active state.
Starts with registration of a READ command with auto precharge
enabled and ends when t RP has been met. Once t RP is met, the bank
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when t RP has been met. Once t RP is met, the bank
will be in the idle state.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
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