- 您现在的位置：买卖IC网 > PDF目录4481 > MT48H8M16LFB4-75:K TR (Micron Technology Inc)IC SDRAM 128MBIT 133MHZ 54VFBGA PDF资料下载
参数资料
| 型号： | MT48H8M16LFB4-75:K TR |
| 厂商： | Micron Technology Inc |
| 文件页数： | 37/63页 |
| 文件大小： | 0K |
| 描述： | IC SDRAM 128MBIT 133MHZ 54VFBGA |
| 标准包装： | 1 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 SDRAM |
| 存储容量： | 128M（8Mx16） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 54-VFBGA |
| 供应商设备封装： | 54-VFBGA（8x8） |
| 包装： | 标准包装 |
| 其它名称： | 557-1531-6 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页当前第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页
128Mb: x16 Mobile SDRAM
Truth Tables
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. For a READ without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the READ on bank n , CL later (see Figure 10 on
page 20).
9. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the READ on bank n when registered (see
Figure 12 and Figure 13 on page 22). DQM should be used one clock prior to the WRITE
command to prevent bus contention.
10. Burst in bank n continues as initiated.
11. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the WRITE on bank n when registered (see
Figure 20 on page 26), with the data-out appearing CL later. The last valid WRITE to bank n
will be data-in registered one clock prior to the READ to bank m .
12. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered (see
Figure 18 on page 25). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m .
13. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
burst has been interrupted by bank m ’s burst.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the READ on bank n , CL later (see Figure 27 on page 31).
The PRECHARGE to bank n will begin when the READ to bank m is registered.
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the READ on bank n when registered (see Figure 28 on
page 31). DQM should be used two clocks prior to the WRITE command to prevent bus con-
tention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered.
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later (see Figure 29 on page 32). The PRECHARGE to bank n will begin after
t WR is met, where t WR begins when the READ to bank m is registered. The last valid WRITE
bank n will be data-in registered one clock prior to the READ to bank m .
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE
to bank n will begin after t WR is met, where t WR begins when the WRITE to bank m is reg-
istered (see Figure 30 on page 32). The last valid WRITE to bank n will be data registered
one clock to the WRITE to bank m .
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
相关PDF资料 |
PDF描述 |
|---|---|
| HSM44DRYI | CONN EDGECARD 88POS DIP .156 SLD |
| HMM44DRYI | CONN EDGECARD 88POS DIP .156 SLD |
| RSC49DRYI-S734 | CONN EDGECARD 98POS DIP .100 SLD |
| RMC49DRYI-S734 | CONN EDGECARD 98POS DIP .100 SLD |
| EP4CGX30BF14C8 | IC CYCLONE IV GX FPGA 30K 169FBG |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48H8M16LFB4-8 | 制造商:Micron Technology Inc 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA |
| MT48H8M16LFB4-8 IT | 制造商:Micron Technology Inc 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA |
| MT48H8M16LFB4-8 IT TR | 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
发布紧急采购，3分钟左右您将得到回复。