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参数资料
| 型号： | MT48H8M16LFB4-75:K TR |
| 厂商： | Micron Technology Inc |
| 文件页数： | 42/63页 |
| 文件大小： | 0K |
| 描述： | IC SDRAM 128MBIT 133MHZ 54VFBGA |
| 标准包装： | 1 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 SDRAM |
| 存储容量： | 128M（8Mx16） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 54-VFBGA |
| 供应商设备封装： | 54-VFBGA（8x8） |
| 包装： | 标准包装 |
| 其它名称： | 557-1531-6 |
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128Mb: x16 Mobile SDRAM
Notes
Notes
1. All voltages referenced to V SS .
2. This parameter is sampled. V DD , V DD Q = +1.8V; T A = 25°C; ball under test biased at
1.4V. f = 1 MHz.
3. I DD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. When the device is in self refresh mode, the on-chip refresh oscillator and address
counters are enabled.
5. The minimum specifications are used only to indicate cycle time at which proper
operation is ensured over the full temperature range (0°C –70°C standard,
–40°C– 85°C for IT).
6. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (V DD and V DD Q must be pow-
ered up simultaneously. V SS and V SS Q must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the t REF refresh require-
ment is exceeded.
7. AC characteristics assume t T = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
sit between V IH and V IL (or between V IL and V IH ) in a monotonic manner.
9. Outputs measured for 1.8V at 0.9V with equivalent load:
Q
20pF
10. t HZ defines the time at which the output achieves the open circuit condition; it is not
a reference to V OH or V OL . The last valid data element will meet t OH before going
High-Z.
11. AC timing and I DD tests have V IL and V IH , with timing referenced to V IH /2 = crossover
point. If the input transition time is longer than t T (MAX), then the timing is refer-
enced at V IL (MAX) and V IH (MIN) and no longer at the V IH /2 crossover point.
12. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid V IH or V IL levels.
13. I DD specifications are tested after the device is properly initialized.
14. Timing actually specified by t CKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by t WR plus t RP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by t WR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The I DD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Address transitions average one transition every 2 clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on t CK = 7.5ns for -75 and t CK = 8ns for -8.
22. V IH overshoot: V IH (MAX) = V DD Q + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. V IL undershoot: V IL (MIN) = –2V for
a pulse width ≤ 3ns.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48H8M16LFB4-8 | 制造商:Micron Technology Inc 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA |
| MT48H8M16LFB4-8 IT | 制造商:Micron Technology Inc 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA |
| MT48H8M16LFB4-8 IT TR | 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
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