- 您现在的位置：买卖IC网 > PDF目录4481 > MT48H8M16LFB4-75:K TR (Micron Technology Inc)IC SDRAM 128MBIT 133MHZ 54VFBGA PDF资料下载
参数资料
| 型号： | MT48H8M16LFB4-75:K TR |
| 厂商： | Micron Technology Inc |
| 文件页数： | 29/63页 |
| 文件大小： | 0K |
| 描述： | IC SDRAM 128MBIT 133MHZ 54VFBGA |
| 标准包装： | 1 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 SDRAM |
| 存储容量： | 128M（8Mx16） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 54-VFBGA |
| 供应商设备封装： | 54-VFBGA（8x8） |
| 包装： | 标准包装 |
| 其它名称： | 557-1531-6 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页
128Mb: x16 Mobile SDRAM
Operation
Deep Power-Down
Deep power-down mode is a maximum power savings feature achieved by shutting off
the power to the entire memory array of the device. Data in the memory array will not be
retained once deep power-down mode is executed. Deep power-down mode is entered
by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH at the
rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep power-
down.
In order to exit deep power-down mode, CKE must be asserted HIGH. Upon exit of deep
power-down mode a full Mobile SDRAM initialization sequence, is required.
Clock Suspend
The clock suspend mode is entered when a column access/burst is in progress and CKE
is registered LOW. In the clock suspend mode, the internal clock is deactivated,
“freezing” the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls at the time of
a suspended internal clock edge is ignored; any data present on the DQ balls remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 25 and Figure 26 on page 30.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
Figure 25:
Clock Suspend During WRITE Burst
T0
T1
T2
T3
T4
T5
C LK
C KE
INTERNAL
C LO C K
C OMMAND
NOP
WRITE
NOP
NOP
ADDRE SS
BANK,
C OL n
D IN
D IN
n
D IN
n +1
D IN
n +2
DON ’ T C ARE
Notes:
1. BL = 4 or greater, and DM is LOW.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
相关PDF资料 |
PDF描述 |
|---|---|
| HSM44DRYI | CONN EDGECARD 88POS DIP .156 SLD |
| HMM44DRYI | CONN EDGECARD 88POS DIP .156 SLD |
| RSC49DRYI-S734 | CONN EDGECARD 98POS DIP .100 SLD |
| RMC49DRYI-S734 | CONN EDGECARD 98POS DIP .100 SLD |
| EP4CGX30BF14C8 | IC CYCLONE IV GX FPGA 30K 169FBG |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48H8M16LFB4-8 | 制造商:Micron Technology Inc 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA |
| MT48H8M16LFB4-8 IT | 制造商:Micron Technology Inc 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA |
| MT48H8M16LFB4-8 IT TR | 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
发布紧急采购，3分钟左右您将得到回复。