参数资料
型号: NAND256W3A0AN6F
厂商: NUMONYX
元件分类: PROM
英文描述: 32M X 8 FLASH 3V PROM, 35 ns, PDSO48
封装: 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件页数: 11/58页
文件大小: 1406K
代理商: NAND256W3A0AN6F
NAND128-A, NAND256-A
Bus operations
19/58
4.4
Data output
Data output bus operations read the data in the memory array, the status register, the
electronic signature, and the serial number.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
characteristics for operations for details of the timings requirements.
4.5
Write protect
Write protect bus operations protect the memory against program or erase operations.
When the Write Protect signal is Low the device does not accept program or erase
operations, therefore, the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection, even during power-up.
4.6
Standby
When Chip Enable is High the memory enters standby mode: the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5.
Bus operations
Bus operation
E
AL
CL
R
W
WP
I/O0 - I/O7
I/O8 - I/O15(1)
1.
Only for x16 devices.
Command input
VIL
VIH
Rising
X(2)
2.
WP must be VIH when issuing a program or erase command.
Command
X
Address input
VIL
VIH
VIL
VIH
Rising
X
Address
X
Data input
VIL
VIH
Rising
X
Data input
Data output
VIL
Falling
VIH
X
Data output
Write protect
X
VIL
XX
Standby
VIH
XX
X
Table 6.
Address insertion, x8 devices(1)(2)
1.
A8 is set Low or High by the 00h or 01h command (see Section 6.1: Pointer operations).
2.
Any additional address input cycles are ignored.
Bus
Cycle
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
A7
A6
A5
A4
A3
A2
A1
A0
2nd
A16
A15
A14
A13
A12
A11
A10
A9
3rd
A24
A23
A22
A21
A20
A19
A18
A17
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