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参数资料
| 型号： | NAND256W3A0AN6F |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 32M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| 封装： | 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 |
| 文件页数： | 52/58页 |
| 文件大小： | 1406K |
| 代理商： | NAND256W3A0AN6F |
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Revision history
NAND128-A, NAND256-A
13
Revision history
Table 24.
Document revision history
Date
Version
Revision details
06-Jun-2003
1
Initial release.
07-Aug-2003
2
Design phase.
27-Oct-2003
3
Engineering phase.
03-Dec-2003
4
Document promoted from Target Specification to Preliminary Data status.
VCC changed to VDD and ICC to IDD.
Changed title of Table 2: Product description and page program typical
timing for NANDXXXR3A devices corrected. Table 1: NAND128-A and
NAND256-A device summary, inserted on page 2.
13-Apr-2004
5
WSOP48 and VFBGA55 packages added, VFBGA63 (9 x 11 x 1mm)
removed.
Figure 19., Cache Program Operation, modified and note 2 modified.
References removed from Section 13: Revision history section and
reference made to ST website instead.
electronic signature clarified and Figure 26: Read electronic signature AC
waveform, modified. Note 2 to Figure 28: Read C operation, one page AC
waveform removed. Only 00h pointer operations are valid before a cache
program operation. Note added to Figure 30: Block erase AC waveform.
Small text changes.
28-May-2004
6
TFBGA55 package added (mechanical data to be announced). 512-Mbit
dual die devices added. Figure 19., Cache Program Operation modified.
Package code changed for TFBGA63 8.5 x 15 x 1.2 mm, 6x8 ball array,
0.8 mm pitch (1-Gbit dual die devices) in Table 23: Ordering information
02-Jul-2004
7
Cache Program removed from document. TFBGA55 package
specifications added (Figure 40., TFBGA55 8 x 10mm - 6x8 active ball
array - 0.80mm pitch, Package Outline and Table 25., TFBGA55 8 x
10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data).
Test conditions modified for VOL and VOH parameters.
01-Oct-2004
8
Section 6.5: Block erase last address cycle modified. Definition of a bad
block modified in Section 7.1: Bad block management. RoHS compliance
added to Section 1: Description. Figure 2: Logic block diagram modified.
Document promoted from Preliminary Data to Full Datasheet status.
03-Dec-2004
9
Automatic Page 0 Read at power-up option no longer available.
PC Demo board with simulation software removed from list of available
development tools. Section 3.5: Chip Enable (E) paragraph clarified.
相关PDF资料 |
PDF描述 |
|---|---|
| NAND512W3A0AN1T | 64M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND512W3A0AN6T | 64M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND512W3A0BZB1E | 64M X 8 FLASH 3V PROM, 35 ns, PBGA55 |
| NAND512W3A2AZB1E | 64M X 8 FLASH 3V PROM, 35 ns, PBGA55 |
| NAND01GW3A3AZA1T | 128M X 8 FLASH 3V PROM, 12000 ns, PBGA63 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NAND256W3A0AZA6E | 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL 2.7V TO 3.6V 256MBIT 32MX8 12US 55VFBGA - Trays |
| NAND256W3A0AZA6F | 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL 2.7V TO 3.6V 256MBIT 32MX8 12US 55VFBGA - Tape and Reel |
| NAND256W3A0BE06 | 功能描述:闪存 NAND & S.MEDIA FLASH RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| NAND256W3A0BN6E | 制造商:Micron Technology Inc 功能描述:NAND - Trays |
| NAND256W3A0BN6F | 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel |
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