74
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
FPGA Conguration Modes (continued)
5-4488(F).a
Figure 46. Daisy-Chain Conguration Schematic
As seen in
Figure 46, the INIT pins for all of the FPGAs are connected together. This is required to guarantee that
powerup and initialization will work correctly. In general, the DONE pins for all of the FPGAs are also connected
together as shown to guarantee that all of the FPGAs enter the start-up state simultaneously. This may not be
required, depending upon the start-up sequence desired.
Daisy-Chaining with Boundary-Scan
Multiple FPGAs can be congured through the JTAG ports by using a daisy-chain of the FPGAs. This daisy-chain-
ing operation is available upon initial conguration after powerup, after a power-on reset, after pulling the program
pin to reset the chip, or during a reconguration if the EN_JTAG RAM has been set.
All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in
on the positive TCK and out on the negative TCK edges.
An upstream FPGA that has received the preamble and length count outputs a high on TDO until it has received
the appropriate number of data frames so that downstream FPGAs do not receive frame start bit pairs. After load-
ing and retransmitting the preamble and length count to a daisy-chain of downstream devices, the lead device
loads its conguration data frames.
The loading of conguration data continues after the lead device had received its conguration read into TDI of
downstream devices on the positive edge of TCK, and shifted out TDO on the negative edge of TCK.
VDD
EPROM
PROGRAM
OE
CE
M2
M1
M0
DONE
HDC
LDC
RCLK
CCLK
DOUT
DIN
DOUT
DIN
CCLK
DONE
DOUT
INIT
CCLK
VDD
PRGM
HDC
LDC
RCLK
HDC
LDC
RCLK
VDD
ORCA
SERIES
FPGA
SLAVE 2
ORCA
SERIES
FPGA
MASTER
ORCA
SERIES
FPGA
SLAVE 1
A[21:0]
D[7:0]
DONE
M3
M2
M1
M0
VDD
M3
M2
M1
M0
VDD