Lattice Semiconductor
79
Data Sheet
September, 2002
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table38.InternalDeratingfor1.5V(VDD15)
Inadditiontosupplyvoltage,processvariation,andoperatingtemperature,circuitandprocessimprovementsof
theORCASeriesFPGAsovertimewillresultinsignificantimprovementoftheactualperformanceoverthoselisted
foraspeedgrade.Eventhoughlowerspeedgradesmaystillbeavailable,thedistributionofyieldtotimingparam-
etersmaybeseveralspeedgradeshigherthanthatdesignatedonaproductbrand.Designpracticesneedtocon-
siderbest-casetimingparameters(e.g.,delays=0),aswellasworst-casetiming.
Theroutingdelaysareafunctionoffan-outandthecapacitanceassociatedwiththeCIPsandmetalinterconnectin
thepath.Thenumberoflogicelementsthatcanbedriven(fan-out)byPFUsisunlimited,althoughthedelayto
reachavalidlogiclevelcanexceedtimingrequirements.Itisdifficulttomakeaccurateroutingdelayestimatesprior
todesigncompilationbasedonfan-out.ThisisbecausetheCAEsoftwaremaydeleteredundantlogicinsertedby
thedesignertoreducefan-out,and/oritmayalsoautomaticallyreducefan-outbynetsplitting.
ThewaveformtestpointsaregivenintheInput/OutputBufferMeasurementConditionssectionofthisdatasheet.
Thetimingparametersgivenintheelectricalcharacteristicstablesinthisdatasheetfollowindustrypractices,and
thevaluestheyreflectaredescribedbelow.
TJ
(°C)
PowerSupplyVoltage
1.40V
1.425V
1.500V
1.575V
1.6V
–40
0.89
0.87
0.83
0.80
0.79
0
0.93
0.91
0.87
0.82
0.81
25
0.96
0.94
0.89
0.85
0.84
85
1.02
1.00
0.95
0.91
0.90
100
1.04
1.02
0.97
0.93
0.92
125
1.06
1.05
1.00
0.96
0.95