Lattice Semiconductor
51
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Microprocessor Interface (continued)
Table 23. Embedded System Bus/MPI Registers
Note: RO = Read Only, R/W = Read/Write
Table 24. Interrupt Register Space Assignments
Note: RO = Read Only, R/W = Read/Write.
For internal system bus, bit 7 is most signicant bit, for MPI bit 0 is most signicant bit.
Register
Byte
Read/Write Initial Value
Description
00
03-00
RO
—
32-bit device ID
01
07-04
R/W
—
Scratchpad register
02
0B-08
R/W
—
Command register
03
0F-0C
RO
—
Status register
04
13
R/W
—
Interrupt enable register – MPI
12
R/W
—
Interrupt enable register – USER
11
R/W
—
Interrupt enable register – FPSC (unused for FPGAs)
10
RO
—
Interrupt cause register
05
17-14
R/W
—
Readback address register (14 bits)
06
1B-18
RO
—
Readback data register
07
1F-1C
R/W
—
Conguration data register
08
23-20
RO
—
Trap address register
09
27-24
RO
—
Bus error address register
0A
2B-28
RO
—
Interrupt vector 1 predened by conguration bit stream
0B
2F-2C
RO
—
Interrupt vector 2 predened by conguration bit stream
0C
33-30
RO
—
Interrupt vector 3 predened by conguration bit stream
0D
37-34
RO
—
Interrupt vector 4 predened by conguration bit stream
0E
3B-38
RO
—
Interrupt vector 5 predened by conguration bit stream
0F
3F-3C
RO
—
Interrupt vector 6 predened by conguration bit stream
10
43—40
—
Top-left PPLL
11
47—44
—
Top-left HPLL
14
53—50
—
Top-right PPLL
18
63—60
—
Bottom-left PPLL
19
67—64
—
Bottom-left HPLL
1C
73—70
—
Bottom-right PPLL
Byte
bit
Read/Write
Description
13
7-0
R/W
Interrupt Enable Register – MPI
12
7-0
R/W
Interrupt Enable Register – USER
11
7-0
R/W
Interrupt Enable Register – FPSC
10
Interrupt Cause Registers
7RO
USER_IRQ_GENERAL;
6RO
USER_IRQ_SLAVE;
5RO
USER_IRQ_MASTER;
4RO
CFG_IRQ_DATA;
3RO
ERR_FLAG 1
2RO
MPI_IRQ
1RO
FPSC_IRQ_SLAVE;
0RO
FPSC_IRQ_MASTER