Lattice Semiconductor
87
Data Sheet
September, 2002
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table51.PrimaryCLK(PCLK)toOutputDelaywithouton-chipPLLs(Pin-to-Pin)
OR4Exxx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C
< TJ < +85 °C;
CL = 30 p.
Notes:
1. Timingiswithouttheuseofthephase-lockedloops(PLLs).
2. Thisclockdelayisforafullyroutedclocktreethatusestheprimaryclocknetwork.ItincludesboththeLVTTL(3.3V)inputclockbufferdelay,
theclockroutingtothePIOCLKinput,theclock→QoftheFF,andthedelaythroughtheLVTTL(3.3V)dataoutputbuffer.ThePCLKinput
clockisconnectedatthesemi-dedicatedprimaryclockinputpins.
3. FortimingimprovementsusingotherI/Obuffertypesfortheinputclockbufferoroutputdatabuffer,see
Table45and
Table47.5-4846(F).b
Figure49.PrimaryClocktoOutputDelay
Table52.PrimaryCLK(PCLK)toOutputDelayusingon-chipPLLs(Pin-to-Pin)
OR4Exxx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C
< TJ < +85 °C;
CL = 30 p.
Notes:
1. TimingusestheautomaticdelaycompensationmodeofthePLLs.ThefeedbacktothePLLisprovidedbytheglobalsystemclockrouting.
OtherdelayvaluesarepossiblebyusingthephasemodificationsmodeofthePLLinstead.
2. Thisclockdelayisforafullyroutedclocktreethatusestheprimaryclocknetwork.ItincludesboththeLVTTL(3.3V)inputclockbufferdelay,
aPLLblock,theclockroutingtothePIOCLKinput,theclock→QoftheFF,andthedelaythroughtheLVTTL(3.3V)dataoutputbuffer.The
PCLKinputclockisconnectedatthesemi-dedicatedPLLinputpin.
3. FortimingimprovementsusingotherI/Obuffertypesfortheinputclockbufferoroutputdatabuffer,see
Table45and
Table47.Description
Device
Speed
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
PCLKInputPin→OUTPUTPin(LVTTL-12mAFast)
OR4E02
OR4E04
OR4E06
—
9.00
9.24
9.42
—
8.03
8.23
8.41
—
7.28
7.46
7.62
ns
Description
Device
Speed
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
PCLKInputPin→OUTPUTPin(LVTTL-12mAFast)
All
—
5.84
—
5.27
—
4.78
ns
PLLDelayAdjustmentsfromCycleStealing(usedto
reduceclk->outbythemindelayvalueshown):
OneDelayCell
TwoDelayCells
ThreeDelayCells
PLLCDEL1
PLLCDEL2
PLLCDEL3
—
0.89
1.64
2.43
—
0.70
1.29
1.98
—
0.64
1.18
1.80
ns
OUTPUT(30pFLOAD)
Q
D
PCLK
PIOFF