
126
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
680-Pin PBGAM Pinout
Table 71. 680-Pin PBGAM Pinout
BM680
VDDIO
Bank
VREF
Group
I/O
OR4E02
OR4E04
OR4E06
Additional
Function
Pair
A1
—
Vss
—
F5
—
VDD33
—
E4
—
O
PRD_DATA
RD_DATA/TDO
—
E3
—
I
PRESET_N
RESET_N
—
D2
—
I
PRD_CFG_
N
PRD_CFG_
N
PRD_CFG_
N
RD_CFG_N
—
G5
—
I
PPRGRM_N PPRGRM_N PPRGRM_N
PRGRM_N
—
D3
0 (TL)
—
VDDIO0
—
D1
0 (TL)
7
IO
PL2D
PLL_CK0C/HPPLL
L21C_D2
F4
0 (TL)
7
IO
PL2C
PLL_CK0T/HPPLL
L21T_D2
A2
—
Vss
—
F3
0 (TL)
7
IO
PL2B
PL3D
—
L22C_D0
G4
0 (TL)
7
IO
PL2A
PL3C
VREF_0_07
L22T_D0
E2
0 (TL)
7
IO
PL3D
PL4D
D5
L23C_D2
H5
0 (TL)
7
IO
PL3C
PL4C
D6
L23T_D2
E5
0 (TL)
—
VDDIO0
—
E1
0 (TL)
8
IO
PL3B
PL4B
PL5D
—
L24C_D0
F2
0 (TL)
8
IO
PL3A
PL4A
PL5C
VREF_0_08
L24T_D0
J5
0 (TL)
8
IO
PL4D
PL5D
PL6D
HDC
L25C_D3
F1
0 (TL)
8
IO
PL4C
PL5C
PL6C
LDC_N
L25T_D3
A18
—
Vss
—
H4
0 (TL)
8
IO
PL4B
PL5B
PL7D
—
L26C_D0
G3
0 (TL)
8
IO
PL4A
PL5A
PL7C
—
L26T_D0
H3
0 (TL)
9
IO
PL5D
PL6D
PL8D
TESTCFG
L27C_D0
G2
0 (TL)
9
IO
PL5C
PL6C
PL8C
D7
L27T_D0
K5
0 (TL)
9
IO
PL5B
PL7D
PL9D
VREF_0_09
L28C_D3
G1
0 (TL)
9
IO
PL5A
PL7C
PL9C
A17/PPC_A31
L28T_D3
J4
0 (TL)
9
IO
PL6D
PL8D
PL10D
CS0_N
L29C_D1
L5
0 (TL)
9
IO
PL6C
PL8C
PL10C
CS1
L29T_D1
A33
—
Vss
—
J3
0 (TL)
10
IO
PL6B
PL9D
PL11D
—
L30C_D0
H2
0 (TL)
10
IO
PL6A
PL9C
PL11C
—
L30T_D0
H1
0 (TL)
10
IO
PL7D
PL10D
PL12D
INIT_N
L31C_D0
J2
0 (TL)
10
IO
PL7C
PL10C
PL12C
DOUT
L31T_D0
J1
0 (TL)
10
IO
PL7B
PL11D
PL13D
VREF_0_10
L32C_D1
K3
0 (TL)
10
IO
PL7A
PL11C
PL13C
A16/PPC_A30
L32T_D1
L4
7 (CL)
1
IO
PL8D
PL12D
PL14D
A15/PPC_A29
L1C_D1
K2
7 (CL)
1
IO
PL8C
PL12C
PL14C
A14/PPC_A28
L1T_D1
L1
7 (CL)
—
VDDIO7
—
K1
7 (CL)
1
IO
PL8B
PL12B
PL15D
—
L2C_D0
L2
7 (CL)
1
IO
PL8A
PL12A
PL15C
—
L2T_D0
L3
7 (CL)
1
IO
PL9D
PL13D
PL16D
VREF_7_01
L3C_D1
N5
7 (CL)
1
IO
PL9C
PL13C
PL16C
D4
L3T_D1