86
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table49.PrimaryClockSkewtoanyPFUorPIORegister
OR4Exxx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, –40 °C
< TJ < +125 °C.
Table50.SecondaryClocktoOutputDelaywithouton-chipPLLs(Pin-to-Pin)
OR4Exxx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C
< TJ
< +85 °C.; CL = 30 pF.
Notes:
1. Timingiswithouttheuseofthephase-lockedloops(PLLs).
2. Thisclockdelayisforafullyroutedclocktreethatusesthesecondaryclocknetwork.ItincludestheLVTTL(3.3V)inputclockbuffer,the
clockroutingtothePIOCLKinput,theclock→QoftheFF,andthedelaythroughtheLVTTL(3.3V)dataoutputbuffer.AnSCLKinputclock
canbeatanyinputpin.
3. FortimingimprovementsusingotherI/Obuffertypesfortheinputclockbufferoroutputdatabuffer,see
Table45and
Table47.5-4846(F).a
Figure48.SecondaryCLKtoOutputDelay
Description
Device
Speed
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
PrimaryClockSkewInformation(posedgeto
posedgeornegedgetonegedge)
OR4E02
OR4E04
OR4E06
—
85
110
120
—
75
95
105
—
70
90
100
ps
PrimaryClockSkewInformation(posedgeto
posedge,negedgetonegedge,posedgeto
negedgeornegedgetoposedge)
OR4E02
OR4E04
OR4E06
—
265
285
300
—
190
210
220
—
180
200
210
ps
Description
Device
Speed
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
SCLK→ OUTPUTPin(LVTTL-12mAFast,
Outputwithin6PICsofSCLKinput)
All
—
7.22
—
6.70
—
6.06
ns
AdditionalDelaypereachextra6PICsper
clockroutedirection.
All
—
0.36
—
0.38
—
0.34
ns
OUTPUT(30pFLOAD)
Q
D
SCLK
PIOFF