90
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table55.PrimaryCLK(PCLK)Setup/HoldTimewithouton-chipPLLs(Pin-to-Pin)
OR4Exxx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C
< TJ
< +85 °C.
Notes:
1. Thepin-to-pintimingparametersinthistablewillmatchORCAFoundryiftheclockdelaymultiplierinthesetuppreferenceissetto0.95for
setuptimeand1.05forholdtime.
2. Timingiswithouttheuseofthephase-lockedloops(PLLs)orPIOinputFFcyclestealingdelays(whichcanprovidereductionsinsetuptime
attheexpenseofholdtime).
3. Thissetup/holdtimeisforafullyroutedclocktreethatusestheprimaryclocknetwork.ItincludesboththeLVTTL(3.3V)inputclockbuffer
delay,theclockroutingtothePIOCLKinput,thesetup/holdtimeofthePIOFF(withthedatainputdelaydisabled)andtheLVTTL(3.3V)
inputdatabuffertoPIOFFdelay.ThePCLKinputclockisconnectedatthesemi-dedicatedprimaryclockinputpins.
4. FortimingimprovementsusingotherI/Obuffertypesfortheinputclockbufferorinputdatabuffer,see
Table45.5-4847(F).a
Figure52.InputtoPrimaryClockSetup/HoldTime
Description
Device
Speed
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
Input to PCLK Setup Time, Input Data Delay
Enabled
OR4E02
OR4E04
OR4E06
4.37
4.19
4.06
—
4.36
4.21
4.09
—
3.99
3.85
3.75
—
ns
Input to PCLK Setup Time, No Input Data
Delay
OR4E02
OR4E04
OR4E06
0.00
—
0.00
—
0.00
—
ns
Input to PCLK Hold Time, Input Data Delay
Enabled
OR4E02
OR4E04
OR4E06
0.00
—
0.00
—
0.00
—
ns
Input to PCLK Hold Time, No Input Data
Delay
OR4E02
OR4E04
OR4E06
4.93
5.17
5.38
—
4.45
4.66
4.84
—
4.02
4.21
4.37
—
ns
Input Delay Adjustments from PIO Cycle
Stealing (typically used to reduce setup time
by the min value shown):
One Delay Cell
Two Delay Cells
Three Delay Cells
ICYCDEL1
ICYCDEL2
ICYCDEL3
—
0.89
1.64
2.43
—
0.70
1.29
1.98
—
0.64
1.18
1.80
ns
Q
D
PCLK
INPUT
PIOFF