82
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table41.EmbeddedBlockRAM(EBR)TimingCharacteristics(512x18)Quad-PortRAMMode
OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ
=+85 °C.
Note: AcompletelistingofEBRTimingParameterscanbedisplayedinORCAFoundry2001orlater.Thisisasamplingofthekeytiming
parameters.
Table 42. Supplemental Logic and Interconnect Cell (SLIC) Timing Characteristics
OR4Exxindustrial:VDD15=1.425V,VDD33=3.0V,TJ
=+85°C.
Note: AcompletelistingofSLICTimingParameterscanbedisplayedinORCAFoundry2001orlater.Thisisasamplingofthekeytiming
parameters.
Parameter
Symbol
Speed
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
Write Operation for RAM Mode:
Maximum Write Clock Frequency
Write Data to Write Clock Setup Time
Write Address to Write Clock Setup Time
EBRWCLK_FRQ
D*_CKW*_SET
A*_CKW*_SET
—
0.28
0.40
200.0
—
0.31
0.38
217.0
—
0.28
0.35
225.0
—
MHz
ns
Async Read Operation for RAM Mode:
Data Out Valid After Read Address
EBR_RA_DEL
—
6.38
—
6.00
—
5.46
ns
Sync Read Operation for RAM Mode:
Maximum Read Clock Frequency
Read Address to Read Clock Setup Time
(OUTREG Mode)
Read Clock to Data Out (IOREG or OUT-
REG modes)
EBRRCLK_FRQ
AR*_CKR*_SET
CKR*_Q*_DEL
—
200.0
3.61
3.05
—
217.0
3.45
2.84
—
225.0
3.13
2.59
MHz
ns
Parameter
Symbol
Speed
Unit
-1
-2
-3
Min
Max
Min Max Min Max
3-Statable BIDIs
BIDI Buffer Delay
BIDI 3-state Enable/Disable Delay
BUF_DEL
TRI_DEL
—
0.35
0.39
—
0.35
—
0.32
ns
Decoder
Decoder Delay (BR[9:8], BL[9:8] to DEC)
DEC_DEL
—
0.89
—
0.81
—
0.73
—