46
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Special Function Blocks (continued)
The MODE signal is generated from the decode of the instruction register. When the MODE signal is high
(EXTEST), the scan data is propagated to the output buffer. When the MODE signal is low (BYPASS or SAMPLE),
functional data from the FPGA’s internal logic is propagated to the output buffer.
The boundary-scan description language (BSDL) is provided for each device in the ORCA Series of FPGAs on the
ORCA Foundry CD. The BSDL is generated from a device prole, pinout, and other boundary-scan information.
5-2844(F).a
Figure 29. Boundary-Scan Cell
Boundary-Scan Timing
To ensure race-free operation, data changes on specic clock edges. The TMS and TDI inputs are clocked in on the
rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST
instruction, parallel data is output from the BSR to the FPGA pads on the falling edge of TCK. The maximum fre-
quency allowed for TCK is 20 MHz.
Figure 30 shows timing waveforms for an instruction scan operation. The diagram shows the use of TMS to
sequence the TAPC through states. The test host (or BSM) changes data on the falling edge of TCK, and it is
clocked into the DUT on the rising edge.
D
Q
D
Q
D
Q
D
Q
P_OUT
HOLI
BIDIRECTIONAL DATA CELL
I/O BUFFER
DIRECTION CONTROL CELL
MODE
UPDATE/TCK
SCAN OUT
TCK
SHIFTN/CAPTURE
P_TS
P_IN
PAD_IN
PAD_TS
PAD_OUT
0
1
0
1
0
1
0
1
0
1
D
Q
D
Q
SCAN IN
0
1
CAPTURE CELL
INBS (TO FPGA ARRAY)