Data Sheet
September, 2002
Lattice Semiconductor
41
ORCA Series 4 FPGAs
Special Function Blocks (continued)
5-6765(F)
Figure 26. Boundary-Scan Interface
D[7:0]
INTR
MICRO-
PROCESSOR
D[7:0]
CE
RA
R/W
DAV
INT
SP
TMS0
TCK
TDI
TDO
TDI
TMS
TCK
TDO
ORCA
SERIES
FPGA
TDI
ORCA
SERIES
FPGA
TMS
TCK
TDO
TDI
TMS
TCK
TDO
ORCA
SERIES
FPGA
BOUNDARY-
SCAN
MASTER
(BSM)
(DUT)
The boundary-scan support circuit shown in
Figure 26is the 497AA boundary-scan master (BSM). The BSM
off-loads tasks from the test host to increase test
throughput. To interface between the test host and the
DUTs, the BSM has a general MPI and provides paral-
lel-to-serial/serial-to-parallel conversion, as well as
three 8K data buffers. The BSM also increases test
throughput with a dedicated automatic test-pattern
generator and with compression of the test response
with a signature analysis register. The PC-based
boundary-scan test card/software allows a user to
quickly prototype a boundary-scan test setup.
Boundary-Scan Instructions
The Series 4 boundary-scan circuitry supports a total
of 18 instructions. This includes ten IEEE 1149.1,
1149.2, and 1532/D1 instructions, one optional IEEE
1149.3 instruction, two IEEE 1532/D1 optional instruc-
tions, and ve ORCA-dened instructions. There are
also 16 other scan chain instructions that are used only
during factory device testing and will not be discussed
in this data sheet. A 6-bit wide instruction register sup-
ports all the instructions listed in
Table 18.The BYPASS instruction passes data intentionally from
TDI to TDO after being clocked by TCK.
Table 18. Boundary-Scan Instructions
Code
Instruction
000000
EXTEST
000001
SAMPLE
000011
PRELOAD
000100
RUNBIST
000101
IDCODE
000110
USERCODE
001000
ISC_ENABLE
001001
ISC_PROGRAM
001010
ISC_NOOP
001011
ISC_DISABLE
001101
ISC_PROGRAM_USERCODE
001110
ISC_READ
010001
PLC_SCAN_RING1
010010
PLC_SCAN_RING2
010011
PLC_SCAN_RING3
010100
RAM_WRITE
010101
RAM_READ
111111
BYPASS