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参数资料
| 型号： | PC34708VM |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA206 |
| 封装： | 13 X 13 MM, 0.80 MM PITCH, LEAD FREE, MO-275HHAC-1, MAPBGA-206 |
| 文件页数： | 116/200页 |
| 文件大小： | 5160K |
| 代理商： | PC34708VM |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
22
PC34708
General IC Functional Description and Application Information
Functional Description
The PC34708 PMIC provides the timekeeping, based on an integrated low power oscillator running with a standard watch crystal.
This oscillator is used for internal clocking, the control logic, and as a reference for the switcher PLL. The timekeeping includes
time of day, calendar, and alarm, and is backed up by coin cell. The clock is driven to the processor for reference and deep sleep
mode clocking.
6.4.4
Miscellaneous Functions
A four wire touch screen interface is integrated with the GP ADC.
A Global reset function disables the charger, powers down the application, resets all registers to their default values, and then
powers it back on.
The mini/micro USB interface automatically identifies the charger type and sets the appropriate battery charge level. It also auto
detects and muxes USB/audio/UART on the USB D+/D- signals.
6.4.5
Interrupt Handling
6.4.5.1
Control
The system is informed about important events, based on interrupts. Unmasked interrupt events are signaled to the processor
by driving the INT pin high; this is true whether the communication interface is configured for SPI or I2C.
Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each
interrupt can be cleared by writing a 1 to the appropriate bit in the Interrupt Status register, which will also cause the interrupt line
to go low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high.
Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high,
the interrupt line will not go high. A masked interrupt can still be read from the Interrupt Status register. This gives the processor
the option of polling for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the
device to determine if any interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked
interrupt bit was already high, the interrupt line will go high after unmasking.
The sense registers contain status and input sense bits, so the system processor can poll the current state of interrupt sources.
They are read only, and not latched or clearable.
Interrupts generated by external events are debounced. Therefore, the event needs to be stable throughout the debounce period
before an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary table following
later in this section. Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly.
6.4.5.2
INTERRUPT BIT SUMMARY
Table 9 summarizes all interrupt, mask, and sense bits associated with INT control. For more detailed behavioral descriptions,
refer to the related chapters.
Table 9. Interrupt, Mask and Sense Bits
Interrupt
Mask
Sense
Purpose
Trigger
Debounce
Time
ADCDONEI
ADCDONEM
-
ADC has finished requested conversions
L2H
0
TSDONEI
TSDONEM
-
Touch screen has finished conversion
L2H
0
TSPENDET
TSPENDETM
-
Touch screen pen detect
Dual
1.0 ms
USBOVP
USBOVPM
USBOVPS
VBUS over-voltage
Sense is 1 if above threshold
Dual
Programmable
SUP_OVP_DB
AUXOVP
AUXOVPM
AUXOVPS
Aux charge over-voltage
Sense is 1 if above threshold
Dual
Programmable
SUP_OVP_DB
WKVBUSDET
WKVBUSDETM
-
Weak VBUS charger detected
H2L
0
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