
Analog Integrated Circuit Device Data
Freescale Semiconductor
124
PC34708
Functional Block Requirements and Behaviors
Control Interface SPI/I2C Block Description and Application Information
7.11.2 Register Set structure
The general structure of the register set is given in the following table. Expanded bit descriptions are included in the following
functional sections for application guidance. For brevity’s sake, references are occasionally made herein to the register set as
the “SPI map” or “SPI bits”, but note that bit access is also possible through the I2C interface option so such references are
implied as generically applicable to the register set accessible by either interface.
7.11.3 SPI Interface
The IC contains a SPI interface port which allows access by a processor to the register set. Via these registers the resources of
the IC can be controlled. The registers also provide status information about how the IC is operating, as well as information on
external signals.
Because the SPI interface pins can be reconfigured for reuse as an I2C interface, a configuration protocol mandates that the CS
pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin). The state of CS is latched in during
the initialization phase of a Cold Start sequence, ensuring that the I2C bus is configured before the interface is activated. With
Table 121. SPI / I2C Bus Configuration
Pin Name
SPI Mode Functionality
I2C Mode Functionality
CS
Configuration
(71), Chip Select
CLK
SPI Clock
SCL: I2C bus clock
MISO
Master In, Slave Out (data output)
SDA: Bi-directional serial data line
MOSI
Master Out, Slave In (data input)
A0 Address Selection
(73)Notes
71.
CS held low at Cold Start, configures the interface for SPI mode; once activated, CS functions as the SPI Chip Select.
72.
CS tied to VCOREDIG at Cold Start, configures the interface for I2C mode; the pin is not used in I2C mode, other than for configuration.
73.
In I2C mode, the MOSI pin is hardwired to ground, or VCOREDIG is used to select between two possible addresses.
Table 122. Register Set
Register
0
Interrupt Status 0
16
Memory A
32
Regulator Mode 0
48
ADC5
1
Interrupt Mask 0
17
Memory B
33
GPIOLV0 Control
49
ADC6
2
Interrupt Sense 0
18
Memory C
34
GPIOLV1 Control
50
ADC7
3
Interrupt Status 1
19
Memory C
35
GPIOLV2 Control
51
Battery Profile
4
Interrupt Mask 1
20
RTC Time
36
GPIOLV3 Control
52
Charger Debounce
5
Interrupt Sense 1
21
RTC Alarm
37
USB Timing
53
Charger Source
6
Power Up Mode Sense
22
RTC Day
38
USB Button
54
Charger LED Control
7
Identification
23
RTC Day Alarm
39
USB Control
55
PWM Control
8
Regulator Fault Sense
24
Switcher 1 A/B Voltage
40
USB Device Type
56
Unused
9
ACC 0
25
Switcher 2 & 3 Voltage
41
Unused
57
Unused
10
ACC 1
26
Switcher 4 A/B Voltage
42
Unused
58
Unused
11
ACC 2
27
Switcher 5 Voltage
43
ADC 0
59
Unused
12
Unused
28
Switcher 1 & 2 Mode
44
ADC 1
60
Unused
13
Power Control 0
29
Switcher 3, 4 and 5 Mode
45
ADC 2
61
Unused
14
Power Control 1
30
Regulator Setting 0
46
ADC 3
62
Unused
15
Power Control 2
31
SWBST Control
47
ADC4
63
Unused