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参数资料
| 型号： | PC34708VM |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA206 |
| 封装： | 13 X 13 MM, 0.80 MM PITCH, LEAD FREE, MO-275HHAC-1, MAPBGA-206 |
| 文件页数： | 30/200页 |
| 文件大小： | 5160K |
| 代理商： | PC34708VM |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
125
PC34708
Functional Block Requirements and Behaviors
Control Interface SPI/I2C Block Description and Application Information
the CS pin held low during startup (as would be the case if connected to the CS driver of an unpowered processor due to the
integrated pull down), then the bus configuration will be latched for SPI mode.
The SPI port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. The
addressable register map spans 64 registers of 24 data bits each. The map is not fully populated, but it follows the legacy
conventions for bit positions corresponding to common functionality with previous generation FSL products.
7.11.3.1 SPI Interface Description
For a SPI read, the first bit sent to the IC must be a zero indicating a SPI read cycle. Next, the six bit address is sent MSB first.
This is followed by one dead bit to allow for more address decode time. The PC34708 will clock the above bits in on the rising
edge of the SPI clock. Then the 24 data bits are driven out on the MISO pin on the falling edge of the SPI clock so the master
can clock them in on the rising edge of the SPI clock.
For each MOSI SPI transfer, first a one is written to the write/read_b bit if this SPI transfer is to be a write. A zero is written to the
write/read_b bit if this is to be a read command. If a zero is written, then any data sent after the address bits are ignored and the
internal contents of the field addressed do not change when the 32nd CLK is sent.
For a SPI write the first bit sent to the PC34708 must be a one indicating a SPI write cycle. Next the six bit address is sent MSB
first. This is followed by one dead bit to allow for more address decode time. Then the data is sent MSB first. The SPI data is
written to the SPI register whose address was sent at the start of the SPI cycle on the falling edge of the 32nd SPI clock.
Additionally, whenever a SPI write cycle is taking place the SPI read data is shifted out for the same address as for the write
cycle. Next the 6-bit address is written, MSB first. Finally, data bits are written, MSB first. Once all the data bits are written then
the data is transferred into the actual registers on the falling edge of the 32nd CLK.
The CS polarity is active high. The CS line must remain high during the entire SPI transfer. For a write sequence it is possible for
the written data to be corrupted, if after the falling edge of the 32nd clock the CS goes low before it's required time. CS can go
low before this point and the SPI transaction will be ignored, but after that point the write process is started and cannot be stopped
because the write strobe pulse is already being generated and CS going low may cause a runt pulse that may or may not be wide
enough to clock all 24 data bits properly. To start a new SPI transfer, the CS line must be toggled low and then pulled high again.
The MISO line will be tri-stated while CS is low.
The register map includes bits that are read/write, read only, read/write “1” to clear (i.e., Interrupts), and clear on read, reserved,
and unused. Refer to the SPI/I2C Register Map and the individual subcircuit descriptions to determine the read/write capability
of each bit. All unused SPI bits in each register must be written to as zeroes. A SPI read back of the address field and unused
bits are returned as zeroes. To read a field of data, the MISO pin will output the data field pointed to by the 6 address bits loaded
at the beginning of the SPI sequence.
Figure 35. SPI Transfer Protocol Single Read/Write Access
CS
CLK
MOSI
MISO
Write_En
Address5
Address4
Address3
Address2
Address 1
Address 0
Data 23
D ata 1
Data 0
Data 23
D ata 1
Data 0
D ata 22
“D ead Bit”
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