
Analog Integrated Circuit Device Data
Freescale Semiconductor
58
PC34708
Functional Block Requirements and Behaviors
Buck Switchers Block Description and Application Information
In addition to controlling the operating mode in Standby, the voltage setting can be changed. The transition in voltage is handled
has an associated set of SPI bits for Standby mode set points. By default, the Standby settings are identical to the non-standby
settings which are initially defined by PUMSx programming.
The actual operating mode of the switchers as a function of the STANDBY pin is not reflected through the SPI. In other words,
the SPI will read back what is programmed in SWxMODE[3:0], not the actual state that may be altered as described previously.
Two tables follow for mode control in the low power Off states. Note that a low power Off activated SWx should use the Standby
set point as programmed by SWxSTBY[4:0]. The activated switcher(s) will maintain settings for mode and voltage until the next
startup event. When the respective time slot of the startup sequencer is reached for a given switcher, its mode and voltage
settings will be updated the same as if starting out of the Off state (except that switchers active through a low power Off mode
will not be off when the startup sequencer is started).
In normal steady state operating mode, the SW1xPWGD pin is high. When the buck charger set point is changed to a higher or
lower set point, the SW1xPWGD pin will go low and will go high again when the higher/lower set point is reached.
7.3.2
Buck Switcher Supplies
Five buck switchers are provided with integrated power switches and synchronous rectification. In a typical application, SW1 and
SW2 are used for supplying the application processor core power domains. Split power domains allow independent DVS control
for processor power optimization, or to support technologies with a mix of device types with different voltage ratings. SW3 is used
for powering internal processor memory as well as low voltage peripheral devices and interfaces which can run at the same
voltage level. SW4A/B is used for powering external DDR memory as well as low voltage peripheral devices and interfaces, which
can run at the same voltage level. Switcher 5 is used to supply the I/O domain for the system.
The buck switchers are supplied from the system supply BP, which is drawn from the main battery or the battery charger (when
present).
1011
PWMPS
APS
1100
APS
PFM
1101
PWM
PFM
1110
PWMPS
PFM
1111
PFM
Table 54. Switcher Control In Memory Hold
SWxMHMODE
Memory Hold Operational Mode (46) 0
Off
1
PFM
Notes:
46.
For Memory Hold mode, an activated SWx should use the
Standby set point as programmed by SWxSTBY[4:0].
Table 55. Switcher Control In User Off
SWxUOMODE
User Off Operational Mode (47) 0
Off
1
PFM
Notes:
47.
For User Off mode, an activated SWx should use the Standby
set point as programmed by SWxSTBY[4:0].
Table 53. Switcher Mode Control for Normal and Standby Operation