
Analog Integrated Circuit Device Data
Freescale Semiconductor
75
PC34708
Functional Block Requirements and Behaviors
5 V Boost Switcher Block Description and Application Information
The switchers have a strong sourcing and sinking capability in the PWM mode. Therefore, the rising/falling slope is determined
by the switcher in PWM mode, however, if the switchers are programmed in PFM, PWMPS, or APSKIP mode during a DVS
transition, the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced,
controlled DVS transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode
operation.
Voltage transitions programmed through SPI(SWx[4:0]) on SW3 and SW5 will step in increments of 25 mV per 4.0
μs, SW4A/B
will step in increments of 25 mV per 8.0
μs when SW4xHI[1:0]=00, and SW4A/B will step in increments of 25 mV per 16 μs when
SW4xHI[1:0]≠00. Additionally, SW3, SW4/B, and SW5 include standby mode set point programmability.
The following diagram shows the general behavior for the switchers when initiated with SPI programming or standby control.
SW1 and SW2 also contain Power Good (outputs from the PC34708 to the application processor). The power good signal is an
active high signal. When SWxPWRGDB is high, it means that the switcher output has reached its programmed voltage. The
SWxPWRGDB voltage outputs will be low during the DVS period and if the current limit is reached on the switcher. The
SWxPWRGD will be low from a low to high or a high to low transition of the switcher output voltage. During the DVS period, the
over-current condition on the switcher should be masked. If the current limit is reached outside of a DVS period, the SWxPWRGD
pin will stay low until the current limit condition is removed.
Figure 18. Voltage Stepping with DVS
7.4
5 V Boost Switcher Block Description and Application
Information
7.4.1
Introduction
SWBST is a boost switching regulator with a programmable output, which defaults to 5.0 V on power up, operating at 2.0 MHz.
SWBST supplies the VUSB regulator for the USB PHY in OTG mode, as well as the VBUS voltage. Note that the parasitic
leakage path for a boost switcher will cause the output voltage SWBSTOUT and SWBSTFB to sit at a Schottky drop below the
battery voltage whenever SWBST is disabled. The switching NMOS transistor is integrated on-chip. An external fly back Schottky
diode, inductor, and capacitor are required.
Actual
Output Voltage
Example
Actual Output
Voltage
Possible
Output Voltage
Window
Internally
Controlled Steps
Output Voltage
with light Load
Initial
Set Point
Voltage
Change
Request
Internally
Controlled Steps
Output
Voltage
Requested
Set Point
Initiated by SPI Programming,Standby Control
Request for
Higher Voltage
Request for
Lower Voltage
SWxP WGD