
QuadFALCTM
PEF 22554 E
T1/J1 Registers
Data Sheet
466
Rev. 1.2, 2006-01-26
PLB
2
rw
Payload Loop-Back
Note: PLB is logically ored with the loop switching performed by
automatic loop switching by BOM messages.
0B
Normal operation. Payload loop is disabled.
1B
The payload loop-back loops the data stream from the receiver
section back to transmitter section. Looped data is output on pin
RDO. Data received on port XDI, XSIG, SYPX and XMFS is
ignored. With FMR4.TM = 1B all 193-bits per frame are looped back.
If FMR4.TM = 0B the DL- or FS- or CRC-bits are generated
internally. AIS is sent immediately on port RDO by setting the
FMR2.SAIS bit. During payload loop is active the receive time slot
offset (registers RC(1:0)) should not be changed. It is
recommended to write the actual value of XC1 into this register
once again, because a write access to register XC1 sets the
read/write pointer of the transmit elastic buffer into its optimal
position to ensure a maximum wander compensation (the write
operation forces a slip).
AXRA
1
rw
Automatic Transmit Remote Alarm
0B
Normal operation
1B
The remote alarm (yellow alarm) bit is set automatically in the
outgoing data stream if the receiver is in asynchronous state
(FRS0.LFA bit is set). In synchronous state the remote alarm bit is
reset.
EXZE
0
rw
Excessive Zeros Detection Enable
Selects error detection mode in the bipolar receive bit stream.
0B
Only bipolar violations are detected.
1B
Bipolar violations and zero strings of 8 or more contiguous zeros in
B8ZS code or more than 15 contiguous zeros in AMI code are
detected additionally and counted in the code violation counter
CVC.
Table 111
MCSP/SSP Constant Values (Case 1)
Name and Description
Value
Synchronization/Resynchronization Procedure (F12/F72)
Specified number of errors in both FT framing and FS framing lead to loss of sync
(FRS0.LFA is set). In the case of FS-bit framing errors, bit FRS0.LMFA is set additionally. A
complete new synchronization procedure is initiated to regain pulseframe alignment and
then multiframe alignment.
00B
Field
Bits
Type
Description