QuadFALC
TM
PEF 22554 E
Functional Description E1/T1/J1
Data Sheet
102
Rev. 1.2, 2006-01-26
Figure 22
Flexible Master Clock Unit
3.4.6.1
PLL (Reset and Configuring)
If the (asynchronous) microcontroller interface mode is selected by IM1 and IM the PLL must be configured either
By programming of the registers GCM5 and GCM6 in “flexible master clocking mode”. Every change of the
contents of these registers - the divider factors N and M of the PLL - causes a reset of the PLL. Switching
between E1 and T1 modes in arbitrary channels causes a reset of the clock unit but not of the PLL itself.
Or by enabling of the ” fixed mode”: GCM2.VFREQ_EN = 0
B (GCM2_E). Programming of registers GCM5 and
GCM6 is not necessary. Any programming of GCM5 and GCM6 does NOT cause a reset of the PLL. Switching
between E1 and T1 modes (for all channels) causes a reset of the clock unit but not of the PLL itself.
The SPI and SCI are synchronous interfaces and therefore need defined clocks immediately after reset, before
any device configuration is done. To enable access to serial interfaces, the clock MCLK must be active and must
have a defined frequency before reset becomes inactive. Depending on the supplied MCLK frequency the internal
PLL must be configured if the SCI- or SPI-Interface mode is selected by IM1 and IM. This can be performed either
By strapping of the pins D(15:5) if “flexible master clocking mode” is enabled (GCM2.VFREQ_EN = 1
B), see
also Table 3. Because the “flexible master clocking mode” is enabled after reset, pinstrapping at D(15:5) is
always necessary! Every status change of the signals at these pins causes a reset of the PLL. Configuring by
the registers GCM5 and GCM6 has no effect and does not cause a reset of the main PLL
Or by usage of the ”clocking fixed mode” (GCM2.VFREQ_EN = 0
B). This is only allowed if the values of N and
M defined by pinstrapping are identical to that values which are internally used for the “clocking fixed mode”.
This avoids changing of N and M by switching into the ”clocking fixed mode” and therefore a new reset of the
PLL. (A reset of the PLL can cause a reset of the hole transceiver! Clock and data processing will be
interrupted.) The used values of N and M in “clocking fixed mode” are: N = 33
10, M = 010. This requires the
pinstrapping configuration to be: D(10:5) = HLLLLH, D(15:11) = LLLLL. In ”clocking fixed mode” further
programming of the registers GCM1 to GCM8 is no longer necessary. The pinstrapping configuration at the
pins D(15:5) do not have any effect. Changing of these values does NOT cause a reset of the PLL. Switching
between E1 and T1 modes causes a reset of the clock unit but not of the main PLL itself.
The configuration of the PLL by pinstrapping (see Table 3) in case of serial interface modes is done in the same
way as by using the registers GCM5 and GCM6 if asynchronous micro controller interface mode (Intel or Motorola)
is selected. Calculation of the values to be configured by pinstrapping can be done also by using the formulas
described for the registers GCM6_E or GCM6_T respectively or by using the “flexible Master Clock Calculator”
which is part of the software support of the QuadFALC
TM, see Chapter 13.3. If the serial interfaces are selected, pinstrapping of D(15:5) configures the PLL directly, so changes causes a direct reset of the PLL.
The conditions to trigger a reset of the central clock PLL are listed in Table 13. Every reset of the PLL causes a
reset of the clock system.
Flexible Master Clock Unit
GCM1...GCM6
MCLK
E1 Clocks
T1 / J1
Clocks
PLL
channel
1 to 4
IM1,IM
D(15:5)
QFALCv3_master_clock_unit