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FALC
56
PEF 2256 H/E
Functional Description T1/J1
User’s Manual
Hardware Description
149
DS1.1, 2003-10-23
5.2.6.1
Synchronization Procedures
For multiframe synchronization the FAS-bits are observed. Synchronous state is
reached if at least one framing candidate is definitely found, or the synchronizer is forced
to lock onto the next available candidate (FMR0.FRS).
In the synchronous state the framing bits (FAS-bits) are observed. The following
conditions selected by FMR4.SSC1/0 lead to the asynchronous state:
Two errors within 4/5/6 framing bits
Two or more erroneous framing bits within one ESF multiframe
More than 320 CRC6 errors per second interval (FMR5.SSC2)
4 incorrect (1 out of 6) consecutive multiframes independent of CRC6 errors.
There are four multiframe synchronization modes selectable using FMR2.MCSP and
FMR2.SSP.
FMR2.MCSP/SSP = 00: In the synchronous state, the setting of FMR0.FRS or
FMR0.EXLS resets the synchronizer and initiates a new frame search. The
synchronous state is reached again, if there is only one definite framing candidate. In
the case of repeated apparent simulated candidates, the synchronizer remains in the
asynchronous state.
In asynchronous state, setting bit FMR0.FRS induces the synchronizer to lock onto
the next available framing candidate if there is one. At the same time the internal
framing pattern memory is cleared and other possible framing candidates are lost.
FMR2.MCSP/SSP = 01: Synchronization is achieved when 3 consecutive multiframe
pattern are correctly found independent of the occurrence of CRC6 errors. If only one
15
16
17
18
19
20
21
22
23
24
2702
2895
3088
3231
3474
3667
3860
4053
4246
4439
–
0
–
–
–
1
–
–
–
1
m
–
m
–
m
–
m
–
m
–
–
–
–
e
5
–
–
–
e
6
–
–
C
D
Table 36
Multiframe
Frame Number
Extended Superframe Structure (F24, ESF; T1/J1)
(cont’d)
F-Bits
Multiframe
Bit Number
FAS
Signaling
Channel
Designation
Assignments
DL
CRC