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FALC
56
PEF 2256 H/E
T1/J1 Registers
User’s Manual
Hardware Description
356
DS1.1, 2003-10-23
Common Configuration Register 2 (Read/Write)
Value after reset: 00
H
Unused bits have to be cleared.
RADD
Receive Address Pushed to RFIFO - HDLC Channel 1
If this bit is set, the received HDLC address information (1 or 2 bytes,
depending on the address mode selected by MODE.MDS0) is pushed
to RFIFO. This function is applicable in non-auto mode and
transparent mode 1. RADD must be set, if SS7 mode is selected.
RBFE
Receive BOM Filter Enable - HDLC Channel 1
Setting this bit the bit oriented message (BOM) receiver only accepts
BOM frames after detecting 7 out of 10 equal BOM pattern. The BOM
pattern is stored in the RFIFO adding a receive status byte marking a
BOM frame (RSIS.HFR) and an interrupt ISR0.RME is generated.
The current state of the BOM receiver is indicated in register SIS.IVB.
When the valid BOM pattern disappears an interrupt ISR0.BIV is
generated.
RCRC
Receive CRC on/off - HDLC Channel 1
Only applicable in non-auto mode.
If this bit is set, the received CRC checksum is written to RFIFO
(CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last bytes in
the received frame, is followed in the RFIFO by the status information
byte (contents of register RSIS). The received CRC checksum is
additionally checked for correctness. If non-auto mode is selected,
the limits for “valid frame” check are modified (refer to
RSIS.VFR).
XCRC
Transmit CRC on/off - HDLC Channel 1
If this bit is set, the CRC checksum is not generated internally. It has
to be written as the last two bytes in the transmit FIFO (XFIFO). The
transmitted frame is closed automatically with a closing flag.
Note: The FALC
56 does not check whether the length of the frame,
i.e., the number of bytes to be transmitted, makes sense or
not.
7
0
CCR2
RADD
RBFE
RCRC
XCRC
(0A)