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FALC
56
PEF 2256 H/E
Functional Description E1
User’s Manual
Hardware Description
65
DS1.1, 2003-10-23
The intrinsic jitter generated in the absence of any input jitter is not more than 0.035 UI.
In digital bipolar line interface mode the clock and data recovery requires HDB3 coded
signals with 50% duty cycle.
4.1.6
Receive Line Coding (E1)
The HDB3 line code or the AMI coding is provided for the data received from the ternary
or the dual rail interface. All code violations that do not correspond to zero substitution
rules are detected. If a bit error causes a code violation that leads to a valid substitution
pattern, this code violation is not detected and the substitution pattern is replaced by the
corresponding zero pattern. The detected errors increment the 16-bit code violation
counter. In case of the optical interface a selection between the NRZ code and the CMI
Code (1T2B) with HDB3 or AMI postprocessing is provided. If CMI code is selected the
receive route clock is recovered from the data stream. The CMI decoder does not correct
any errors. In case of NRZ coding data is latched with the falling edge of signal RCLKI.
The HDB3 code is used along with double violation detection or extended code violation
detection (selectable by FMR0.EXZE)). In AMI code all code violations are detected. The
detected errors increment the 16-bit code violation counter.
When using the optical interface with NRZ coding, the decoder is bypassed and no code
violations are detected.
Table 11
Clock Source
RCLK Output Selection (E1)
RCLK Frequency
CMR1.
DCS
×
CMR1.
RS1/0
00
Receive Data
(2.048 Mbit/s on RL1/RL2,
RDIP/RDIN or ROID)
Receive Data
in case of LOS
2.048 MHz
(recovered clock)
Constant high
2.048 MHz
(generated by DCO-R,
synchronized on SYNC)
2.048 MHz
8.192 MHz
0
1
01
10
DCO-R
×
×
10
11