FALC
56
PEF 2256 H/E
Operational Description T1/J1
User’s Manual
Hardware Description
204
DS1.1, 2003-10-23
SIC1
SIC2,
SIC3
00
H
00
H
00
H
2.048 MHz system clocking rate, receive buffer 2 frames,
transmit buffer bypass, data sampled or transmitted on
the falling edge of SCLKR/X, automatic freeze signaling,
data is active in the first channel phase
loop-backs are disabled.
Remote alarm indication towards remote end is disabled.
LFA condition: 2 out of 4/5/6 framing bits, non-auto-
synchronization mode, F12 multiframing, internal bit
robbing access disabled
The transmit clock slot offset is cleared.
The transmit time slot offset is cleared.
The receive clock slot offset is cleared.
The receive time slot offset is cleared.
Idle channel code is cleared.
Normal operation (no “Idle Channels” selected).
Normal operation (no clear channel operation).
Slave mode, local loop off,
analog interface selected, remote loop off
pulse count for LOS detection cleared
pulse count for LOS recovery cleared
40
H
,03
H
,7B
H
Transmit pulse mask (transmitter in tristate mode)
FF
H
All interrupts are disabled
00
H
Internal second timer, power on
00
H
RCLK output: DPLL clock, DCO-X enabled, DCO-X
internal reference clock
00
H
SCLKR selected, SCLKX selected, receive
synchronization pulse sourced by SYPR, transmit
synchronization pulse sourced by SYPX
00
H
SEC port input active high
00
H,
00
H
00
H,
00
H
Input function of ports XP(A to D): SYPX
LOOP
FMR4
FMR5
00
H
00
H
00
H
XC0
XC1
RC0
RC1
IDLE
ICB(3:1)
CCB(3:1)
LIM0
LIM1
PCD
PCR
XPM(2:0)
IMR(5:0)
GCR
CMR1
00
H
9C
H
00
H
9C
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
CMR2
GPC1
PC(4:1)
Input function of ports RP(A to D): SYPR,
Table 54
Initial Values after reset and FMR1.PMOD = 1 (T1/J1)
(cont’d)
Register
Initiated
Value
Meaning