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FALC
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PEF 2256 H/E
Signaling Controller Operating Modes
User’s Manual
Hardware Description
220
DS1.1, 2003-10-23
Byte sampling in BOM Mode (T1/J1)
a)
b)
Three different BOM reception modes can be programmed (CCR1.BRM, CCR2.RBFE).
10 byte packets:
CCR1.BRM = 0
After storing 10 bytes in RFIFO the receive status byte marking a BOM frame
(RSIS.HFR) is added as the eleventh byte and an interrupt (ISR0.RME) is generated.
The sampling of data bytes continues and interrupts are generated every 10 bytes until
an HDLC flag is detected.
Continuous reception:
CCR1.BRM = 1
Interrupts are generated every 32 (16, 4, 2) bytes. After detecting an HDLC flag, byte
sampling is stopped, the receive status byte is stored in RFIFO and an RME interrupt is
generated.
Reception with enabled BOM filter: CCR2.RBFE = 1
The BOM receiver will only accept BOM frames after detecting 7 out of 10 equal BOM
pattern. The BOM pattern is stored in the RFIFO adding a receive status byte, marking
a BOM frame (RSIS.HFR) and generating an interrupt status ISR0.RME. The current
state of the BOM receiver is indicated in register SIS.IVB. When the valid BOM pattern
disappears an interrupt ISR0.BIV is generated.
The user can switch between these modes at any time. Byte sampling can be stopped
by deactivating the BOM receiver (MODE.BRAC). In this case the receive status byte is
added, an interrupt is generated and HDLC mode is entered. Whether the FALC
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operates in HDLC or BOM mode are checked by reading the signaling status register
(SIS.BOM).
1111
1111 1111 0011 0100 1111 1111 0011 0100 1110 1111 0011 0100 1101 1111
sync
not stored
new sync
1.byte
stored
1.corrupted
sync
2.byte
stored
2.corrupted
sync
corrupted
sync
1111
1111 0111 0110 1101 1111 0111 0110 1111 1111 0111 0110 0111 1111
sync
1.byte
stored
1.corrupted
byte
2.byte
stored
2.sync
3.byte
stored
3.corrupted
sync