FALC
56
PEF 2256 H/E
T1/J1 Registers
User’s Manual
Hardware Description
411
DS1.1, 2003-10-23
RCRC2
Receive CRC ON/OFF - HDLC Channel 2
Only applicable in non-auto mode.
If this bit is set, the received CRC checksum is written to RFIFO2
(CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last bytes in
the received frame, is followed in the RFIFO2 by the status
information byte (contents of register RSIS2). The received CRC
checksum will additionally be checked for correctness. If non-auto
mode is selected, the limits for “valid frame” check are modified.
XCRC2
Transmit CRC ON/OFF - HDLC Channel 2
If this bit is set, the CRC checksum will not be generated internally. It
has to be written as the last two bytes in the transmit FIFO (XFIFO2).
The transmitted frame is closed automatically with a closing flag.
ITF2
Interframe Time Fill - HDLC Channel 2
Determines the idle (= no data to be sent) state of the transmit data
coming from the signaling controller.
0
=
Continuous logical "1" is output
1
=
Continuous flag sequences are output ("01111110" bit patterns)
XMFA2
Transmit Multiframe Aligned - HDLC Channel 2
Determines the synchronization between the framer and the
corresponding signaling controller.
0 =
The contents of the XFIFO2 is transmitted without multiframe
alignment.
1 =
The contents of the XFIFO2 is transmitted multiframe aligned.
RFT12, RFT02
RFIFO2 Threshold Level - HDLC Channel 2
The size of the accessible part of RFIFO2 can be determined by
programming these bits. The number of valid bytes after an RPF
interrupt is given in the following table:
The value of RFT(1:0)2 can be changed dynamically if reception is
not running or after the current data block has been read, but before
the command CMDR3.RMC2 is issued (interrupt controlled data
transfer).
RFT12
0
0
1
1
RFT02
0
1
0
1
Size of Accessible Part of RFIFO2
32 bytes (default value)
16 bytes
4 bytes
2 bytes