FALC
56
PEF 2256 H/E
T1/J1 Registers
User’s Manual
Hardware Description
448
DS1.1, 2003-10-23
XMB
Transmit Multiframe Begin
This bit is set with the beginning of a transmitted multiframe related to
the internal transmit line interface timing.
SUEX
Signaling Unit Error Threshold Exceeded - HDLC Channel 1
Masks the indication by interrupt that the selected error threshold for
SS7 signaling units has been exceeded.
0 =
Signaling unit error count below selected threshold
1 =
Signaling unit error count exceeded selected threshold
Note:SUEX is only valid, if SS7 mode is selected.
If SUEX is caused by an aborted/invalid frame, the interrupt
will be issued regularly until a valid frame is received (e.g. a
FISU).
XLSC
Transmit Line Status Change
XLSC is set with the rising edge of the bit FRS1.XLO or with any
change of bit FRS1.XLS.
The actual status of the transmit line monitor can be read from the
FRS1.XLS and FRS1.XLO.
XPR
Transmit Pool Ready - HDLC Channel 1
A data block of up to 32 bytes can be written to the transmit FIFO.
XPR enables the fastest access to XFIFO. It has to be used for
transmission of long frames, back-to-back frames or frames with
shared flags.
Interrupt Status Register 2 (Read)
All bits are reset when ISR2 is read.
If bit GCR.VIS is set, interrupt statuses in ISR2 are flagged although they are masked by
register IMR2. However, these masked interrupt statuses neither generate a signal on
INT, nor are visible in register GIS.
FAR
Frame Alignment Recovery
The framer has reached synchronization. Set with the falling edge of
bit FRS0.LFA.
It is set also after alarm simulation is finished and the receiver is still
synchronous.
7
0
ISR2
FAR
LFA
MFAR
LMFA
AIS
LOS
RAR
RA
(6A)