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FALC
56
PEF 2256 H/E
Operational Description E1
User’s Manual
Hardware Description
195
DS1.1, 2003-10-23
6
Operational Description E1
6.1
Operational Overview E1
The FALC
56 can be operated in two modes, which are either E1 mode or T1/J1 mode.
The device is programmable via a microprocessor interface which enables byte or word
access to all control and status registers.
After reset the FALC
56 must be initialized first. General guidelines for initialization are
described in
Chapter 6.3
.
The status registers are read-only and are updated continuously. Normally, the
processor reads the status registers periodically to analyze the alarm status and
signaling data.
6.2
Device Reset E1
The FALC
56 is forced to the reset state if a low signal is input on pin RES for a minimum
period of 10 μs. During reset the FALC
56 needs an active clock on pin MCLK. All output
stages are in a high-impedance state, all internal flip-flops are reset and most of the
control registers are initialized with default values.
SIgnals (for example RL1/2 receive line) should not be applied before the device is
powered up.
After reset the device is initialized to E1 operation.
6.3
Device Initialization in E1 Mode
After reset, the FALC
56 is initialized for doubleframe format with register values listed
in the following table.
Table 47
Register
GCM(8:1)
FMR0
FMR1
FMR2
Initial Values after Reset (E1)
Reset Value
Meaning
all 00
H
2.048 MHz on pin MCLK.
00
H
NRZ Coding, no alarm simulation.
00
H
E1-doubleframe format, 2 Mbit/s system data rate, no AIS
transmission to remote end or system interface, payload
loop off.
00
H
00
H
00
H
falling edge of SCLKR/X, automatic freeze signaling, data
is active in the first channel phase
SIC1
SIC2,
SIC3
8.192 MHz system clocking rate, receive buffer 2 frames,
transmit buffer bypass, data sampled or transmitted on the