FALC
56
PEF 2256 H/E
User’s Manual
Hardware Description
16
DS1.1, 2003-10-23
Preface
The FALC
56 framer and line interface component is designed to fulfill all required
interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100
bus.
The digital functions as well as the analog characteristics are configured via a flexible
microprocessor interface.
Organization of this Document
This User’s Manual is organized as follows:
Chapter 1
,
Introduction
Gives a general description of the product and its family, lists the key features, and
presents some typical applications.
Chapter 2
,
External Signals
Lists pin locations with associated signals, categorizes signals according to function,
and describes signals.
Chapter 3
to
Chapter 5
,
Functional Description E1/T1/J1
These chapters describe the functional blocks and principle operation modes,
organized into separate sections for E1 and T1/J1 operation
Chapter 6
and
Chapter 7
,
Operational Description E1/T1/J1
Shows the operation modes and how they are to be initialized (separately for E1 and
T1/J1).
Chapter 8
,
Signaling Controller Operating Modes
Describes signaling controller functions for both E1 and T1/J1 operation.
Chapter 9
and
Chapter 10
,
E1 Registers
and
T1/J1 Registers
Gives a detailed description of all implemented registers and how to use them in
different applications/configurations.
Chapter 11
,
Electrical Characteristics
Specifies maximum ratings, DC and AC characteristics.
Chapter 12
,
Package Outlines
Shows the mechanical values of the device packages.
Chapter 13
,
Appendix
Gives an example for overvoltage protection and information about application notes
and other support.
Terminology
References
Index