FALC
56
PEF 2256 H/E
T1/J1 Registers
User’s Manual
Hardware Description
456
DS1.1, 2003-10-23
Receive Signaling Register (Read)
Value after reset: not defined
Table 74
Receive Signaling Registers (T1/J1)
Receive Signaling Register 1 to 12
Each register contains the received bit robbing information for 8 DS0 channels. The
received robbed bit signaling information of a complete ESF multiframe is compared to
the previously received one. In F12/72 frame format the received signaling information
of every 24 frames is compared to the previously received 24 frames. If the contents
changed a Receive Signaling Changed interrupt ISR0.RSC is generated and informs the
user that a new multiframe has to be read within the next 3 ms. Received data is stored
in RS(12:1) registers. The RS1.7 is received in channel 1 frame 1 and RS12.0 in channel
24 frame 24 (ESF).
If requests for reading the RS(12:1) registers are ignored, received data might get lost.
Additionally a receive signaling data change pointer indicates an update of register
RS(12:1). Refer also to register RSP(2:1).
Access to RS(12:1) registers is only valid if the serial receive signaling access on the
system highway is disabled.
7
0
RS1
A1
B1
C1/A2
D1/B2
A2/A3
B2/B3
C2/A4
D2/B4
(70)
RS2
A3/A5
B3/B5
C3/A6
D3/B6
A4/A7
B4/B7
C4/A8
D4/B8
(71)
RS3
A5/A9
B5/B9
C5/A10
D5/B10
A6/A11
B6/B11
C6/A12
D6/B12
(72)
RS4
A7/A13
B7/B13
C7/A14
D7/B14
A8/A15
B8/B15
C8/A16
D8/B16
(73)
RS5
A9/A17
B9/B17
C9/A18
D9/B18
A10/A19
B10/B19 C10/A20 D10/B20
(74)
RS6
A11/A21 B11/B21 C11/A22 D11/B22 A12/A23
B12/B23 C12/A24 D12/B24
(75)
RS7
A13/A1
B13/B1
C13/A2
D13/B2
A14/A3
B14/B3
C14/A4
D14/B4
(76)
RS8
A15/A5
B15/B5
C15/A6
D15/B6
A16/A7
B16/B7
C16/A8
D16/B8
(77)
RS9
A17/A9
B17/B9
C17/A10 D17/B10 A18/A11
B18/B11 C18/A12 D18/B12
(78)
RS10
A19/A13 B19/B13 C19/A14 D19/B14 A20/A15
B20/B15 C20/A16 D20/B16
(79)
RS11
A21/A17 B21/B17 C21/A18 D21/B18 A22/A19
B22/B19 C22/A20 D22/B20
(7A)
RS12
A23/A21 B23/B21 C23/A22 D23/B22 A24/A23
B24/B23 C24/A24 D24/B24
(7B)