![](http://datasheet.mmic.net.cn/330000/PEF2256_datasheet_16444063/PEF2256_402.png)
FALC
56
PEF 2256 H/E
T1/J1 Registers
User’s Manual
Hardware Description
402
DS1.1, 2003-10-23
should be serviced within the next 3 ms. If requests for new information are ignored,
current contents is repeated.
Note: If access to XS(12:1) registers is done without control of the interrupt ISR1.CASE
and the write access to these registers is done exact in that moment when this
interrupt is generated, data is lost.
A software reset (CMDR.XRES) resets these registers.
Port Configuration 1 to 4 (Read/Write)
Value after reset: 00
H
RPC(3:0)
Receive multifunction port configuration
The multifunction ports RP(A to D) are bidirectional. After Reset these
ports are configured as inputs. With the selection of the pin function
the In/Output configuration is also achieved. The input function SYPR
may only be selected once, it must not be selected twice or more.
Register PC1 configures port RPA, while PC2
→
port RPB,
PC3
→
port RPC and PC4
→
port RPD.
0000 = SYPR: Synchronous Pulse Receive (Input)
Together with register RC(1:0) SYPR defines the frame begin
on the receive system interface. Because of the offset
programming the SYPR and the RFM pin function cannot be
selected in parallel.
0001 = RFM: Receive Frame Marker (Output)
CMR2.IRSP = 0 and GPC1.SRFM = 0:
The receive frame marker is active high for one 1.544 MHz
period during any bit position of the current frame.
Programming of the bit position is done by using registers
RC(1:0). The internal time slot assigner is disabled. The RFM
offset calculation formula has to be used.
CMR2.IRSP = 0 and GPC1.SRFM = 1:
The receive frame marker is active high for one system period
as programmed by SIC1.SSC and SIC2.SSC2 during any bit
7
0
PC1
RPC13
RPC12
RPC11
RPC10
XPC13
XPC12
XPC11
XPC10
(80)
PC2
RPC23
RPC22
RPC21
RPC20
XPC23
XPC22
XPC21
XPC20
(81)
PC3
RPC33
RPC32
RPC31
RPC30
XPC33
XPC32
XPC31
XPC30
(82)
PC4
RPC43
RPC42
RPC41
RPC40
XPC43
XPC42
XPC41
XPC40
(83)