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FALC
56
PEF 2256 H/E
Operational Description T1/J1
User’s Manual
Hardware Description
203
DS1.1, 2003-10-23
7
Operational Description T1/J1
7.1
Operational Overview T1/J1
The FALC
56 can be operated in two principle modes, which are either E1 mode or T1/
J1 mode.
The device is programmable via a microprocessor interface which enables byte or word
access to all control and status registers.
After reset the FALC
56 must be initialized first. General guidelines for initialization are
described in
Chapter 7.3
The status registers are read-only and are updated continuously. Normally, the
processor reads the status registers periodically to analyze the alarm status and
signaling data.
7.2
Device Reset T1/J1
The FALC
56 is forced to the reset state if a low signal is input on pin RES for a minimum
period of 10 μs. During reset the FALC
56 needs an active clock on pin MCLK. All output
stages are in a high-impedance state, all internal flip-flops are reset and most of the
control registers are initialized with default values.
SIgnals (for example RL1/2 receive line) should not be applied before the device is
powered up.
After reset the device is initialized to E1 operation.
7.3
Device Initialization in T1/J1 Mode
After reset, the FALC
56 is initialized for E1 doubleframe format. To initialize T1/J1
mode, bit FMR1.PMOD has to be set high. After the internal clocking is settled to T1/
J1mode (takes up to 20 μs), the following register values are initialized:
.
Table 54
Initial Values after reset and FMR1.PMOD = 1 (T1/J1)
Register
Initiated
Value
all 00
H
00
H
00
H
00
H
Meaning
GCM(8:1)
FMR0
FMR1
FMR2
1.544 MHz on pin MCLK.
NRZ coding, no alarm simulation
PCM24 mode, 2.048 Mbit/s system data rate, no AIS
transmission to remote end or system interface, payload
loop off, channel translation mode 0