
RELEASED
DATA SHEET
PM7366 FREEDM-8
ISSUE 4
PMC-1970930
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
177
Register 0x388 : THDL Indirect Channel Data #2
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
R/W
7BIT
0
Bit 14
R/W
PRIORITYB
0
Bit 13
R/W
INVERT
0
Bit 12
R/W
DFCS
0
Bit 11
Unused
X
Bit 10
Unused
X
Bit 9
Unused
X
Bit 8
W
FLEN[8]
0
Bit 7
W
FLEN[7]
0
Bit 6
W
FLEN[6]
0
Bit 5
W
FLEN[5]
0
Bit 4
W
FLEN[4]
0
Bit 3
W
FLEN[3]
0
Bit 2
W
FLEN[2]
0
Bit 1
W
FLEN[1]
0
Bit 0
W
FLEN[0]
0
This register contains data to be inserted into the channel provision RAM in an indirect write
operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
FLEN[8:0]:
The indirect FIFO length (FLEN[8:0]) is the number of blocks, less one, that is provisioned to
the circular channel FIFO specified by the FPTR[8:0] block pointer. The FIFO length to be
written to the channel provision RAM, in an indirect channel write operation, must be set up in
this register before triggering the write.