
RELEASED
DATA SHEET
PM7366 FREEDM-8
ISSUE 4
PMC-1970930
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
242
All 8 framers in the TOCTL should be programmed to operate in “Clock Master: NxDS0” mode in
both the ingress and egress direction.
13.3 JTAG Support
The FREEDM-8 supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1
standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS,
TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB
input is the active low reset signal used to reset the TAP controller. TCK is the test clock used to
sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the
TAP controller through its states. The basic boundary scan architecture is
shown below.
Figure 20 – Boundary Scan Architecture
Boundary Scan
Register
Control
TDI
TDO
Device Identification
Register
Bypass
Register
Instruction
Register
and
Decode
TRSTB
TMS
TCK
Test
Access
Port
Controller
Mux
DFF
Select
Tri-state Enable
The boundary scan architecture consists of a TAP controller, an instruction register with instruction
decode, a bypass register, a device identification register and a boundary scan register. The TAP