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参数资料
| 型号： | QL5842-33BPSN484M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA484 |
| 封装： | 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAJ-1, BGA-484 |
| 文件页数： | 12/76页 |
| 文件大小： | 1409K |
| 代理商： | QL5842-33BPSN484M |
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2006 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. K
2
Architecture Overview
The QL58x2 device family of QuickPCI Embedded Standard Products (ESPs) provides a complete and
customizable PCI interface solution combined with programmable logic. Since the QL58x2 devices provide
optimized pre-verified PCI cores, the burden of PCI timing closure and PCI protocol compliance has been
eliminated and allows for the maximum 32-bit PCI bus bandwidth (264 MBps).
The programmable logic portion of this family contains up to 1,348 QuickLogic Logic Cells and up to 22
QuickLogic Dual-Port RAM Blocks. These configurable RAM blocks can be configured in many width/depth
combinations. They can also be combined with logic cells to form FIFOs, or be initialized via Serial EEPROM
on power-up and used as ROMs.
The QL58x2 device meets PCI 2.3 electrical and timing specifications and has been fully hardware-tested. The
QL58x2 device features 1.8 V operation with multi-volt compatible I/Os. The device can easily operate in 3 V
embedded systems and is fully compatible with 3.3 V applications.
PCI Controller
The PCI Controller is a 33/66 MHz 32-bit PCI 2.3 compliant Master/Target Controller capable of infinite
length Master Write and Read transactions at zero wait states (264 MBps).
The Master will never insert wait states during transfers, so data is supplied or received by FIFOs that can be
configured in the programmable region of the device. The Master is capable of initiating any type of PCI
commands, including configuration cycles and Memory Write and Invalidate (MWI). This enables the QL58x2
device family to act as a PCI host. The Master Controller will most often be operated by a DMA Controller in
the programmable region of the device. DMA Controller reference design is available and is included in the
QuickWorks design software.
The Target interface offers full PCI Configuration Space and flexible target addressing. It supports zero-wait-
state target Write and one-wait-state target Read operations. It also supports retry, disconnect with/without
data transfer, and target abort requested by the back end. Any number of 32-bit BARs may be configured as
either memory or I/O space. All required and optional PCI 2.3 Configuration Space registers can be
implemented within the programmable region of the device. A reference design of a Target Configuration and
Addressing module is available and is included in the QuickWorks design software.
The interface ports are divided into a set of ports for master transactions and a set for target transactions. The
Master DMA controller and Target Configuration Space and Address Decoding are done in the programmable
logic region of the device. These functions are not timing critical, so leaving these elements in the
programmable region allows the greatest degree of flexibility to the designer. Reference DMA controller,
Configuration Space, and Address Decoding blocks are readily available so that the design cycle can be
minimized.
Table 1 shows several commonly implemented IP cores in the programmable logic portion of the
Master/Target Controller device. Their respective logic cell utilization and performance information are shown
clearly for easy reference. Notice that the Configuration Space/Address Decoding and DMA Controller IP
cores are labelled as essential IP cores. These IP blocks are necessary for the Master/Target Controller to be
fully functional. The optional IP cores are common interface IP cores made available so that designers may
implement according to their design requirements. These optional IP cores do not affect the functionality of
the Master/Target Controller.
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