参数资料
型号: QL5842-33BPSN484M
厂商: QUICKLOGIC CORP
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, PBGA484
封装: 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAJ-1, BGA-484
文件页数: 32/76页
文件大小: 1409K
代理商: QL5842-33BPSN484M
2006 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. K
38
NOTE: When using a PLL, t
PGCK and tBGCK are effectively zero due to delay adjustment by Phase Locked
Loop feedback path.
Figure 35: Global Clock Structure Timing Elements
Figure 36: Dual-Port SRAM Cell
Table 22: QL58x2 Device Family Global Clock Delay
Clock Segment
Parameter
Value
Min
Max
tPGCK
Global clock pin delay to quad net
-
1.92 ns
tBGCK
Global clock tree delay (quad net to flip-flop)
-
0.28 ns
tPGCK
tBGCK
Internally generated clock, or
clock from general routing network
Global Clock
(CLK) Input
Quad-Net Clock Network
FF
Global Clock Buffer
WA
WD
WE
WC LK
RE
RC LK
RA
RD
RAM Module
[9:0]
[17:0]
[9:0]
[17:0]
AS Y NC R D
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