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参数资料
| 型号： | QL5842-33BPSN484M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA484 |
| 封装： | 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAJ-1, BGA-484 |
| 文件页数： | 56/76页 |
| 文件大小： | 1409K |
| 代理商： | QL5842-33BPSN484M |
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2006 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. K
6
PCI Target Interface
Mst_RdData_Valid
O
Master Read data valid on Usr_Addr_WrData[31:0]. This serves as the PUSH control for
the external FIFO (in FPGA region) that receives data from the PCI32 core.
Mst_RdBurst_Done
O
Master Read transaction is completed. Active for only one clock cycle.
Flush_FIFO
I
Internal FIFO flush. FIFO flushed immediately after it is active (synchronized with PCI
clock).
Mst_LatCntEn
I
Enable Latency Counter. Set to 0 to ignore the Latency Timer in the PCI configuration
space (offset 0Ch). For full PCI compliance, this port should be always set to 1.
Mst_Xfer_D1
O
Data was transferred on the previous PCI clock. Useful for updating DMA transfer
counts on DMA Read operations.
Mst_Last_Cycle
O
Active during the last data transfer of a master transaction
Mst_REQN
O
Copy of the PCI REQN signal generated by QL58x2 as PCI master. Not usually used in
the back-end design.
Mst_IRDYN
O
Copy of the PCI IRDYN signal generated by QL58x2 as PCI master. Valid only when
QL58x2 is the PCI master. Kept low otherwise. Not usually used in the back-end design.
Mst_Tabort_Det
O
Target abort detected during master transaction. This is normally an error condition
handled in the DMA controller.
Mst_TTO_Det
O
Target timeout detected (no response from target). This is normally an error condition
handled in the DMA controller.
Table 3: PCI Target Interface
Signal
I/O
Description
Usr_Addr_WrData[31:0]
O
Target address, and target Write data. During all target accesses, the address is
presented on Usr_Addr_WrData[31:0]; at the same time, Usr_Adr_Valid is active.
During target Write transactions, this port also presents valid Write data to the PCI
configuration space or user logic when Usr_Adr_Inc is active.
Usr_CBE[3:0]
O
PCI command and byte enables. During target accesses, the PCI command is
presented on Usr_CBE[3:0]; at the same time, Usr_Adr_Valid is active. This port also
presents active-low byte enables to the PCI configuration space or user logic.
Usr_Adr_Valid
O
Indicates the beginning of a PCI transaction, and that a target address is valid on
Usr_Addr_WrData[31:0] and the PCI command is valid on Usr_CBE[3:0]. When this
signal is active, the target address must be latched and decoded to determine if this
address belongs to the device's memory or I/O space. Also, the PCI command must be
decoded to determine the type of PCI transaction. On subsequent clocks of a target
access, this signal is low, indicating that address is NOT present on
Usr_Addr_WrData[31:0].
Usr_Adr_Inc
O
Indicates that the target address should be incremented, because the previous data
transfer has completed. During burst target accesses, the target address is only
presented to the back-end logic at the beginning of the transaction (when
Usr_Adr_Valid is active), and must therefore be latched and incremented by four for
subsequent data transfers. Note that during target Write transactions, Usr_Adr_Inc
indicates valid data on Usr_Addr_WrData[31:0] that must be accepted by the backend
logic (regardless of the state of Usr_Rdy). During Read transactions, Usr_Adr_Inc
signals to the backend that the PCI core has presented the read data on the PCI bus
(TRDYN asserted).
Table 2: PCI Master Interface (Continued)
Signal
I/O
Description
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