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参数资料
| 型号： | QL5842-33BPSN484M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA484 |
| 封装： | 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAJ-1, BGA-484 |
| 文件页数： | 7/76页 |
| 文件大小： | 1409K |
| 代理商： | QL5842-33BPSN484M |
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2006 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. K
15
Phase Locked Loop (PLL) Information
Instead of requiring extra components, designers simply need to instantiate one of the pre-configured models
(described in this section). The QuickLogic built-in PLLs support a wider range of frequencies than many other
PLLs. These PLLs also have the ability to support different ranges of frequency multiplications or divisions,
driving the device at a faster or slower rate than the incoming clock frequency. When PLLs are cascaded, the
clock signal must be routed off-chip through the PLLPAD_OUT pin prior to routing into another PLL; internal
routing cannot be used for cascading PLLs.
Figure 7 illustrates a QuickLogic PLL.
Figure 7: PLL Block Diagram
Fin represents a very stable high-frequency input clock and produces an accurate signal reference. This signal
can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass through the PLL itself.
Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external F
in signal and the
local VCO form a control loop. The VCO is multiplied or divided down to the reference frequency, so that a
phase detector (the crossed circle in Figure 7) can compare the two signals. If the phases of the external and
local signals are not within the tolerance required, the phase detector sends a signal through the charge pump
and loop filter (Figure 7). The charge pump generates an error voltage to bring the VCO back into alignment,
and the loop filter removes any high frequency noise before the error voltage enters the VCO. This new VCO
signal enters the clock tree to drive the chip's circuitry.
F
out represents the clock signal emerging from the output pad (the output signal PLLPAD_OUT is explained
in Table 12). The PLL always drives the PLLPAD_OUT signal, regardless of whether the PLL is configured
for on-chip use. The PLLPAD_OUT will not oscillate if PLL_RESET is asserted, or if the PLL is powered down.
Most QuickLogic products contain four PLLs. The PLL presented in Figure 7 controls the clock tree in the
fourth quadrant of its FPGA. QuickLogic PLLs compensate for the additional delay created by the clock tree
itself, as previously noted, by subtracting the clock tree delay through the feedback path.
vco
Filter
FIN
FOUT
+
-
1st Quadrant
2nd Quadrant
3rd Quadrant
4th Quadrant
Clock
Tree
Frequency Divide
Frequency Multiply
1
._.
2
._.
4
._.
4
._.
2
._.
1
.._
PLL Bypass
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