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参数资料
| 型号： | QL5842-33BPSN484M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA484 |
| 封装： | 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAJ-1, BGA-484 |
| 文件页数： | 16/76页 |
| 文件大小： | 1409K |
| 代理商： | QL5842-33BPSN484M |
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2006 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. K
23
Programmable Logic Routing
QL58x2 devices are engineered with six types of routing resources as follows: short (sometimes called
segmented) wires, dual wires, quad wires, express wires, distributed networks, and default wires. Short wires
span the length of one logic cell, always in the vertical direction. Dual wires run horizontally and span the
length of two logic cells. Short and dual wires are predominantly used for local connections. Default wires
supply VCC and GND (Logic ‘1’ and Logic ‘0’) to each column of logic cells.
Quad wires have passive link interconnect elements every fourth logic cell. As a result, these wires are typically
used to implement intermediate length or medium fan-out nets.
Express lines run the length of the device uninterrupted. Each of these lines has a higher capacitance than a
quad, dual, or short wire, but less capacitance than shorter wires connected to run the length of the device.
The resistance will also be lower because the express wires don't require the use of pass links. Express wires
provide higher performance for long routes or high fan-out nets.
Distributed networks are described in Clock Networks on page 21. These wires span the programmable logic
and are driven by quad-net buffers.
Global Power-On Reset (POR)
The QL58x2 device family features a global power-on reset. This reset is hardwired to all registers and resets
them to Logic ‘0’ upon power-up of the device. In QuickLogic devices, the asynchronous Reset input to flip-
flops has priority over the Set input; therefore, the Global POR will reset all flip-flops during power-up. If you
want to set the flip-flops to Logic ‘1’, you must assert the “Set” signal after the Global POR signal has been
deasserted.
Figure 15: Power-On Reset
Low Power Mode
Quiescent power consumption of all QL58x2 family devices can be reduced significantly by de-activating the
charge pumps inside the architecture. By applying 3.3 V to the VPUMP pin, the internal charge pump is de-
activated—this effectively reduces the static and dynamic power consumption of the device. The QL58x2
device family is fully functional and operational in the Low Power mode. Users who have a 3.3 V supply
available in their system should take advantage of this low power feature by tying the VPUMP pin to 3.3 V.
Otherwise, if a 3.3 V supply is not available, this pin should be tied to ground.
VCC
Power-on
Reset
Q
XXXXXXX
0
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