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参数资料
| 型号： | QL5842-33BPSN484M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA484 |
| 封装： | 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAJ-1, BGA-484 |
| 文件页数： | 30/76页 |
| 文件大小： | 1409K |
| 代理商： | QL5842-33BPSN484M |
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2006 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. K
36
AC Characteristics
The AC Specifications (at VCC = 1.8 V, TA = 25° C, Worst Case Corner, Speed Grade = -8 (K = 1.01)) are
provided from Table 21 through Table 30. Logic Cell diagrams and waveforms are provided from Figure 31
through Figure 42.
Figure 31: QL58x2 Device Family
Logic Cell
Table 21: Logic Cells
Symbol
Parameter
Value
Min
Max
t
PD
Combinatorial Delay of the longest path: time taken by the combinatorial circuit
to output
0.28 ns
0.98 ns
tSU
Setup time: time the synchronous input of the flip-flop must be stable before the
active clock edge
0.10 ns
0.25 ns
tHL
Hold time: time the synchronous input of the flip-flop must be stable after the
active clock edge
0 ns
t
CO
Clock-to-out delay: the amount of time taken by the flip-flop to output after the
active clock edge.
0.22 ns
0.52 ns
tCWHI
Clock High Time: required minimum time the clock stays high
0.46 ns
tCWLO
Clock Low Time: required minimum time that the clock stays low
0.46 ns
tSET
Set Delay: time between when the flip-flop is ”set” (high)
and when the output is consequently “set” (high)
0.69 ns
tRESET
Reset Delay: time between when the flip-flop is ”reset” (low) and when the
output is consequently “reset” (low)
1.09 ns
tSW
Set Width: time that the SET signal must remain high/low
0.3 ns
tRW
Reset Width: time that the RESET signal must remain high/low
0.3 ns
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