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参数资料
| 型号： | QL5842-33BPSN484M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA484 |
| 封装： | 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAJ-1, BGA-484 |
| 文件页数： | 45/76页 |
| 文件大小： | 1409K |
| 代理商： | QL5842-33BPSN484M |
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2006 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. K
5
PCI Master Interface
The internal signals used to interface with the PCI controller in the QL58x2 are listed in Table 2 along with a
description of each signal. The direction of the signal indicates if the signal is an input provided by the local
interface (I) or an output provided by the PCI controller (O).
NOTE: Signals that end with the character ‘N’ should be considered active-low (for example, Mst_IRDYN
).
Table 2: PCI Master Interface
Signal
I/O
Description
PCI_cmd[3:0]
I
PCI command to be used for the master transaction. This signal must remain
unchanged throughout the period when Mst_Burst_Req is active. PCI commands
considered as Reads include Interrupt Acknowledge, I/O Read, Memory Read,
Configuration Read, Memory Read Multiple, and Memory Read Line. PCI commands
considered as Writes include Special Cycle, I/O Write, Memory Write, Configuration Write,
Memory Write, and Invalidate.Users should make sure that only valid PCI commands are
supplied.
Mst_Burst_Req
I
Request use of the PCI bus. When it is active, the core requests the PCI bus and then
generates a Master transaction. This signal should be held active until all requested data is
transferred on the PCI bus and deactivated in the 2nd clock cycle following the last data
transfer on PCI (to avoid being considered as requesting a new transaction).
Mst_WrAd[31:0]
I
Address for master DMA writes. This address must be treated as valid from the beginning
of a DMA Write until the DMA Write operation is complete. It should be incremented by four
bytes each time data is transferred on the PCI bus.
Mst_RdAd[31:0]
I
Address for master DMA reads. This address must be treated as valid from the beginning
of a DMA read until the DMA Read operation is complete. It should be incremented by four
bytes each time data is transferred on the PCI bus.
Mst_WrData[31:0]
I
Data for master DMA Writes (to PCI bus).
Mst_BE[3:0]
I
Byte enables for master DMA Reads and writes. Active-low.
Mst_WrData_Valid
I
Data and byte enable valid on Mst_WrData[31:0] (for master Write only) and
Mst_BE[3:0] (for both master Read and Write).
Mst_WrData_Rdy
O
Data receive acknowledge for Mst_WrData[31:0] (for master Write only) and
Mst_BE[3:0] (for both).This serves as the PUSH control for the internal FIFO and the POP
control for the external FIFO (in FPGA region) which provides data and byte enables to the
PCI32 core.
Mst_BE_Sel
I
Byte enable select for master transactions. When low, Mst_BE[3:0] should remain
constant throughout the entire transfer (when Mst_Burst_Req is active) and it is used for
every data phase of the master transaction. When high, Mst_BE[3:0] pushed into internal
FIFO (along with data in case of master Write) is used. Should be held constant throughout
the transaction.
Mst_WrBurst_Done
O
Master Write transaction is completed. Active for only one clock cycle.
Mst_Rd_Term_Sel
I
Master Read termination mode select when Mst_BE_Sel is high. When both
Mst_BE_Sel and Mst_Rd_Term_Sel are high, Master Read termination happens when the
internal FIFO is empty, and Mst_Two_Reads and Mst_One_Read are ignored. When either
signal is low, Mst_Two_Reads and Mst_One_Read are used to signal the end of Master
Read. Should be held constant throughout the transaction.
Mst_One_Read
I
Signals to the PCI32 core that only one data transfer remains to be read in the burst Read.
Mst_Two_Reads
I
Two data transfers remain to be read in the burst Read It is not used for single-data-
phase Master Read transactions.
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