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| 型号： | QL5842-33BPSN484M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA484 |
| 封装： | 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAJ-1, BGA-484 |
| 文件页数： | 8/76页 |
| 文件大小： | 1409K |
| 代理商： | QL5842-33BPSN484M |
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2006 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. K
16
PLL Modes of Operation
QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output frequency—
Table 11 indicates the features of each mode.
NOTE: “HF” stands for “high frequency” and “LF” stands for “low frequency.”
The input frequency can range from 12.5 MHz to 440 MHz, while output frequency ranges from 25 MHz to
220 MHz. When adding PLLs to the top-level design, be sure that the PLL mode matches the desired input
and output frequencies.
PLL Signals
Table 12 summarizes the key signals in QuickLogic PLLs.
NOTE: Because PLLCLK_IN and PLL_RESET signals have PLL_INPAD, and PLLPAD_OUT has OUTPAD,
you do not need to add additional pads to your design.
Table 11: PLL Mode Frequencies
PLL Model
Output Frequency
Input Frequency Range
Output Frequency Range
PLL_HF
Same as input
66 MHz–220 MHz
PLL_LF
Same as input
25 MHz–66 MHz
PLL_MULT2HF
2x
33 MHz–110 MHz
66 MHz–220 MHz
PLL_MULT2LF
2x
12.5 MHz–33 MHz
25 MHz–66 MHz
PLL_DIV2HF
1/2x
220 MHz–440 MHz
110 MHz–220 MHz
PLL_DIV2LF
1/2x
50 MHz–220 MHz
25 MHz–110 MHz
PLL_MULT4
4x
12.5 MHz–50 MHz
50 MHz–200 MHz
PLL_DIV4
1/4x
100 MHz–440 MHz
25 MHz–110 MHz
Table 12: QuickLogic PLL Signals
Signal Name
Description
PLLCLK_IN
Input clock signal
PLL_RESET
Active High Reset If PLL_RESET is asserted, then CLKNET_OUT and PLLPAD_OUT are reset
to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work.
ONn_OFFCHIP
This is a reserved signal. It can be connected to VCC or GND.
CLKNET_OUT
Out to internal gates This signal bypasses the PLL logic before driving the internal gates. Note
that this signal cannot be used in the same quadrant where the PLL signal is used
(PLLCLK_OUT).
PLLCLK_OUT
Out from PLL to internal gates This signal can drive the internal gates after going through the
PLL.
PLLPAD_OUT
Out to off-chip This outgoing signal is used off-chip. The PLLPAD_OUT is always active, driving
the PLL-derived clock signal out through the pad. The PLLPAD_OUT will not oscillate if
PLL_RESET is asserted, or if the PLL is powered down.
LOCK_DETECT
Active High Lock detection signal
NOTE: For simulation purposes, this signal gets asserted after 10 clock cycles. However, it can
take a maximum of 200 clock cycles to sync with the input clock upon release of the PLL_RESET
signal.
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