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参数资料
| 型号： | QL5842-33BPSN484M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA484 |
| 封装： | 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAJ-1, BGA-484 |
| 文件页数： | 67/76页 |
| 文件大小： | 1409K |
| 代理商： | QL5842-33BPSN484M |
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2006 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. K
7
Usr_RdDecode
I
This signal should be the combinatorial decode of the “user read” command from
Usr_CBE[3:0]. This command may be mapped from any of the PCI Read commands,
such as Memory Read, Memory Read Line, Memory Read Multiple, I/O Read, etc. It is
internally gated with Usr_Adr_Valid.
Usr_WrDecode
I
This signal should be the combinatorial decode of the “user write” command from
Usr_CBE[3:0]. This command may be mapped from any of the PCI Write commands,
such as Memory Write or I/O Write. It is internally gated with Usr_Adr_Valid.
Usr_Select
I
This signal should be driven active when the address on Usr_Addr_WrData[31:0] has
been decoded and determined to be within the address space of the device.
Usr_Addr_WrData[31:0] must be compared to each of the valid Base Address
Registers in the PCI configuration space. Also, this signal must be gated by the Memory
Access Enable or I/O Access Enable registers in the PCI configuration space
(Command Register bits 1 or 0 at offset 04h). Internally gated with Usr_Adr_Valid.
Usr_Write
O
This signal is active throughout a “user write” transaction, which has been decoded by
Usr_WrDecode at the beginning of the transaction. The Write strobe for individual
DWORDs of data (on Usr_Addr_WrData[31:0]) during a user Write transaction should
be generated by logically ANDing this signal with Usr_Adr_Inc.
Cfg_Write
O
This signal is active throughout a “configuration write” transaction. The Write strobe for
individual DWORDs of data (on Usr_Addr_WrData[31:0]) during a configuration Write
transaction should be generated by logically ANDing this signal with Usr_Adr_Inc.
Usr_Read
O
This signal is active throughout a “user read” transaction, which has been decoded by
Usr_RdDecode at the beginning of the transaction.
Cfg_Read
O
This signal is active throughout a “configuration read” transaction.
Cfg_RdData[31:0]
I
Data from the PCI configuration registers, required to be presented during PCI
configuration reads.
Usr_RdData[31:0]
I
Data from the back-end user logic required to be presented during PCI user reads.
Cfg_CmdReg3
I
Bit 3 from the Command Register in the PCI configuration space (offset 04h). Enable
Special Cycle monitoring. If high, the core reports data parity error in Special Cycles
through SERRN if Cfg_CmdReg8 is active.
Cfg_CmdReg4
I
Bit 4 from the Command Register in the PCI configuration space (offset 04h). Memory
Write and Invalidate (MWI) Enable. If high, the core generates MWI transactions as
requested by the backend. Otherwise it uses Memory Write instead even if MWI is
requested.
Cfg_CmdReg6
I
Bit 6 from the Command Register in the PCI configuration space (offset 04h). Parity
Error Response. If high, the core uses PERRN to report data parity errors. Otherwise it
never drives it.
Cfg_CmdReg8
I
Bit 8 from the Command Register in the PCI configuration space (offset 04h). SERRN
Enable. If high, the cores uses SERRN to report address parity errors if Cfg_CmdReg6
is high.
Cfg_LatCnt[7:0]
I
8-bit value of the Latency Timer in the PCI configuration space (offset 0Ch).
Usr_MstRdAd_Sel
I
Used when a target Read operation should return the value set on the Mst_RdAd[31:0]
pins. This select pin saves on logic which would otherwise need to be used to multiplex
Mst_RdAd[31:0] into the Usr_RdData[31:0] bus. When this signal is asserted, the data
on Usr_RdData[31:0] is ignored.
Table 3: PCI Target Interface (Continued)
Signal
I/O
Description
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