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参数资料
| 型号： | QL5842-33BPSN484M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA484 |
| 封装： | 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAJ-1, BGA-484 |
| 文件页数： | 48/76页 |
| 文件大小： | 1409K |
| 代理商： | QL5842-33BPSN484M |
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2006 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. K
52
Recommended Unused Pin Terminations for QL58x2 Device Family
All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally using the
Configuration Editor. This option is given in the bottom-right corner of the placement window. To use the
Placement Editor, choose Constraint
> Fix Placement in the Option pull-down menu of SpDE.
The rest of the pins should be terminated at the board level in the manner presented in Table 34.
Table 34: Recommended Unused Pin Terminations
Signal Name
Recommended Termination
PLLOUT<x>a
a. x represents a number.
In earlier versions, the recommendation for unused PLLOUT pins was that they be connected to
VCC or GND. This was acceptable for Rev. D (and earlier) silicon, including all 0.25 m devices.
For Rev. G (and later) silicon this is not correct. Unused PLLOUT pins should be left unconnected.
Used PLLOUT pins will normally be connected to inputs, but can also be left unconnected. For
the truth table of PLLOUT connections, refer to
IOCTRL<y>b
b. y represents an alphabetical character.
There is an internal pulldown resistor to GND on this pin. This pin should be tied to GND if it is
not used. For backwards compatibility with QL5632 and QL5732, it can be tied to VDED or GND.
If tied to VDED, it will draw no more than 20 A per IOCTRL pin due to current through the
pulldown resistor.
CLK/PLLIN<x>
Any unused clock pins should be connected to VDED or GND.
PLLRST<x>
If a PLL module is not used, then the associated PLLRST<x> must be connected to VDED or
GND. If VCCPLL is grounded, then PLLRST must be grounded also. If VCCPLL is driven by 2.5
V or 3.3 V, PLLRST must be driven by the same voltage.
INREF<y>
If an I/O bank does not require the use of the INREF signal the pin should be connected to GND.
Table 35: Recommended PLLOUT Terminations Truth Table
PLL_RESET
Recommended PLLOUT Termination
0
Must be left unconnected.
1
May be left unconnected, or connected to GND. Must not be connected to VCC.
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