- 您现在的位置：买卖IC网 > PDF目录296941 > QL8150-6PT280I (QUICKLOGIC CORP) FPGA, 640 CLBS, 188946 GATES, PBGA280 PDF资料下载
参数资料
| 型号： | QL8150-6PT280I |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| 封装： | 0.80 MM PITCH, LFBGA-280 |
| 文件页数： | 11/96页 |
| 文件大小： | 1607K |
| 代理商： | QL8150-6PT280I |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页
2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
19
Sample/Preload Instruction. The Sample/Preload Instruction allows a device to remain in its functional
mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this
test, the boundary scan register can be accessed through a data scan operation, allowing users to sample
the functional data entering and leaving the device.
Bypass Instruction. The Bypass Instruction allows data to skip a device boundary scan entirely, so the
data passes through the bypass register. The Bypass instruction allows users to test a device without passing
through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial
data to be transferred through a device without affecting the operation of the device.
JTAG BSDL Support
BSDL-Boundary Scan Description Language
Machine-readable data for test equipment to generate testing vectors and software
BSDL files available for all device/package combinations from QuickLogic
Extensive industry support available and ATVG (Automatic Test Vector Generation)
Security Links
There are several security links to disable reading logic from the array, and to disable JTAG access to the
device. Programming these optional links completely disables access to the device from the outside world and
provides an extra level of design security not possible in SRAM-based FPGAs. The option to program these
links is selectable through QuickWorks in the Tools/Options/Device Programming window in SpDE.
Power-Up Loading Link
The flexibility link enables Power-Up Loading of the Embedded RAM blocks. If the link is programmed, the
Power-Up Loading state machine is activated during power-up of the device. The state machine communicates
with an external EPROM via the JTAG pins to download memory contents into the on-chip RAM. If the link
is not programmed, Power-Up Loading is not enabled and the JTAG pins function as they normally would.
The option to program this link is selectable through QuickWorks in the Tools/Options/Device Programming
window in SpDE. For more information on Power-Up Loading, see QuickLogic Application Note 55 at
. See the Power-Up Loading power-up sequencing
requirement for proper functionality in Figure 16.
相关PDF资料 |
PDF描述 |
|---|---|
| QL8150-6PT280M | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-6PTN280C | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-6PTN280I | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-6PTN280M | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-6PUN196C | FPGA, 640 CLBS, 188946 GATES, PBGA196 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL8250 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8250-6PQN208C-5690 | 制造商:QuickLogic Corporation 功能描述: |
| QL8250-6PQN208C-5691 | 制造商:QuickLogic Corporation 功能描述: |
| QL82SD | 制造商:未知厂家 制造商全称:未知厂家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL82SD-PB516 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
发布紧急采购，3分钟左右您将得到回复。