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| 型号： | QL8150-6PT280I |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| 封装： | 0.80 MM PITCH, LFBGA-280 |
| 文件页数： | 23/96页 |
| 文件大小： | 1607K |
| 代理商： | QL8150-6PT280I |
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2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
3
Programmable Logic Architectural Overview
The Eclipse II logic cell structure is presented in Figure 2. This architectural feature addresses today's register-
intensive designs.
The Eclipse II logic cell structure presented in Figure 2 is a dual register, multiplexer-based logic cell. It is
designed for wide fan-in and multiple, simultaneous output functions. Both registers share CLK, SET, and
RESET inputs. The second register has a two-to-one multiplexer controlling its input. The register can be
loaded from the NZ output or directly from a dedicated input.
NOTE: The input PP is not an “input” in the classical sense. It is a static input to the logic cell and selects
which path (NZ or PS) is used as an input to the Q2Z register. All other inputs are dynamic and can
be connected to multiple routing channels.
The complete logic cell consists of two six-input AND gates, four two-input AND gates, seven two-to-one
multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30
(including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six
outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell
accommodates many user functions with a single level of logic delay while other architectures require two or
more levels of delay.
Table 3: Performance Standards
Function
Description
Slowest Speed Grade
Fastest Speed Grade
Multiplexer
16:1
2.8 ns
2.4 ns
Parity Tree
24
3.4 ns
2.9 ns
36
4.6 ns
3.9 ns
Counter
16 bit
275 MHz
328 MHz
32 bit
250 MHz
300 MHz
FIFO
128 x 32
197 MHz
235 MHz
128 x 64
188 MHz
266 MHz
256 x 16
208 MHz
248 MHz
Clock-to-Out
4 ns
3.3 ns
System clock
200 MHz
300 MHz
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PDF描述 |
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| QL8150-6PT280M | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-6PTN280C | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-6PTN280I | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-6PTN280M | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-6PUN196C | FPGA, 640 CLBS, 188946 GATES, PBGA196 |
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