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参数资料
| 型号： | QL8150-6PT280I |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| 封装： | 0.80 MM PITCH, LFBGA-280 |
| 文件页数： | 40/96页 |
| 文件大小： | 1607K |
| 代理商： | QL8150-6PT280I |
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2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
45
INREF(A)
I
Differential reference voltage
The INREF is the reference voltage pin for GTL+, SSTL2, and
STTL3 standards. Follow the recommendations provided in
Table 14 for the appropriate standard. The A inside the
parenthesis means that INREF is located in BANK A. This pin
should be tied to GND if voltage referenced standards are not
used.
PLLOUT
O
PLL output pin
Dedicated PLL output pin. Must be left unconnected if PLL is
powered up and not held in reset, since PLLOUT will be
driving the PLL-derived clock. May be left unconnected if PLL
is held in reset or not powered up. PLLOUT pin is driven by
VCCIO. For a list of each PLLOUT pin and the VCCIO pin that
powers it see
IOCTRL(A)
I
Highdrive input
This pin provides fast RESET, SET, CLOCK, and ENABLE
access to the I/O cell flip-flops, providing fast clock-to-out and
fast I/O response times. This pin can also double as a high-
drive pin to the internal logic cells. The A inside the
parenthesis means that IOCTRL is located in Bank A. There
is an internal pulldown resistor to GND on this pin. This pin
should be tied to GND if it is not used. For backwards
compatibility with Eclipse and EclipsePlus, it can be tied to
VDED or GND. If tied to VDED, it will draw no more than
20 A per IOCTRL pin due to current through the pulldown
resistor. The voltage tolerance of this pin is specified by
VDED. Note that the 208 PQFP package has no I/O control
pins.
VPUMP
I
Charge Pump Disable
This pin disables the internal charge pump for lower static
power consumption. To disable the charge pump, connect
VPUMP to 3.3 V. If the Disable Charge Pump feature is not
used, connect VPUMP to GND. For backwards compatibility
with Eclipse and EclipsePlus devices, connect VPUMP to
GND.
VDED
I
Voltage tolerance for clocks,
TDO JTAG output, and IOCTRL
This pin specifies the input voltage tolerance for CLK,
DEDCLK, PLLIN, and IOCTRL dedicated input pins, as well
as the output voltage drive TDO JTAG pins. If the PLLs are
used, VDED must be the same as VCCPLL. The legal range
for VDED is between 1.71 V and 3.6 V. For backwards
compatibility with Eclipse and EclipsePlus devices, connect
VDED to 2.5 V.
Table 31: Pin Descriptions (Continued)
Pin
Direction
Function
Description
相关PDF资料 |
PDF描述 |
|---|---|
| QL8150-6PT280M | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-6PTN280C | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-6PTN280I | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-6PTN280M | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-6PUN196C | FPGA, 640 CLBS, 188946 GATES, PBGA196 |
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